STM32F103RCT6 定时器相关常用函数

只看该作者 · 2024-3-31 14:49

1. STM32F103RCT6 定时器常用函数
1.1 TIM_TimeBaseInit()：用于初始化定时器基本参数，如预分频值、计数模式、时钟分频因子等。
1.2 TIM_Cmd()：用于启动或停止定时器。
1.3 TIM_SetCounter()：用于设置定时器的计数器值。
1.4 TIM_GetCounter()：用于获取定时器的计数器当前值。
1.5 TIM_ITConfig()：用于使能或禁用定时器中断，并指定中断源及触发条件。
1.6 TIM_ClearITPendingBit()：用于清除定时器中断标志位。
1.7 TIM_OCInit()：用于初始化输出比较通道参数，如输出模式、极性、脉冲宽度等。
1.8 TIM_OCxInit()：用于初始化特定输出比较通道（x=1,2,3,4）的参数。
1.9 TIM_SetCompare1()、TIM_SetCompare2()、TIM_SetCompare3()、TIM_SetCompare4()：用于设置输出比较通道1、2、3、4的脉冲宽度。
1.10 TIM_PWMOutputState()：用于使能或禁用PWM输出信号。
1.11 TIM_CtrlPWMOutputs()：用于使能或禁用PWM模式输出。
1.12 TIM_ETRClockMode2Config()：用于配置外部时钟输入模式。
1.13 TIM_ITRxExternalClockConfig()：用于配置外部时钟计数模式。
1.14 TIM_EncoderInterfaceConfig()：用于配置定时器作为编码器接口的参数，如编码器计数模式、电平极性等。
1.15 TIM_ICInit()：用于初始化输入捕获通道参数，如输入捕获模式、捕获极性、滤波器设置等。
1.16 TIM_SetIC1Prescaler()、TIM_SetIC2Prescaler()、TIM_SetIC3Prescaler()、TIM_SetIC4Prescaler()：用于设置输入捕获通道1、2、3、4的预分频值。
1.17 TIM_SetIC1Filter()、TIM_SetIC2Filter()、TIM_SetIC3Filter()、TIM_SetIC4Filter()：用于设置输入捕获通道1、2、3、4的滤波器参数。
1.18 TIM_GetITStatus 获取中断标志位，该函数用于查询指定定时器产生的中断是否发生，并返回中断状态。

只看该作者 · 2024-3-31 14:49

定时器使用配置流程：
以TIM2为例，介绍STM32定时器的基本使用流程。

2.1 定义一个TIM_TimeBaseInitTypeDef类型的结构体变量并初始化
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
//初始化定时器参数
TIM_TimeBaseStructure.TIM_Period = 1000-1; //设置计数器自动重装值
TIM_TimeBaseStructure.TIM_Prescaler = 72-1; //设置预分频值
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; //设置时钟分割
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; //设置计数器计数模式

2.2 开启TIM2时钟和复位TIM2模块
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); //使能TIM2时钟
TIM_DeInit(TIM2); //复位TIM2模块

2.3 初始化TIM2定时器
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); //初始化TIM2定时器

2.4 使能TIM2更新中断
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE); //打开TIM2的更新中断

2.5 配置NVIC中断优先级
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; //选择TIM2中断通道
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; //抢占优先级为0
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; //子优先级为1
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //使能中断通道

2.6 启动TIM2定时器
TIM_Cmd(TIM2, ENABLE); //启动TIM2定时器

2.7 定义定时器中断服务函数
void TIM2_IRQHandler(void)
{
if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET) //判断是否产生了更新中断
{
TIM_ClearITPendingBit(TIM2, TIM_IT_Update); //清除更新中断标志位
//在这里进行需要执行的操作
}
}

在以上步骤完成之后，即可启动定时器并执行中断服务函数中的操作。需要注意的是，如果需要使用多个定时器，需要对每个定时器各自定义上述流程和中断服务函数。

只看该作者 · 2024-3-31 14:50

TIM_TimeBaseIni

复制

/**

  * [url=home.php?mod=space&uid=247401]@brief[/url]  Initializes the TIMx Time Base Unit peripheral according to 

  *         the specified parameters in the TIM_TimeBaseInitStruct.

  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.

  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef

  *         structure that contains the configuration information for the 

  *         specified TIM peripheral.

  * @retval None

  */

void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)

{

  uint16_t tmpcr1 = 0;



  /* Check the parameters */

  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 

  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));

  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));



  tmpcr1 = TIMx->CR1;  



  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||

     (TIMx == TIM4) || (TIMx == TIM5)) 

  {

    /* Select the Counter Mode */

    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));

    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;

  }

 

  if((TIMx != TIM6) && (TIMx != TIM7))

  {

    /* Set the clock division */

    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));

    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;

  }



  TIMx->CR1 = tmpcr1;



  /* Set the Autoreload value */

  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;

 

  /* Set the Prescaler value */

  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;

    

  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  

  {

    /* Set the Repetition Counter value */

    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;

  }



  /* Generate an update event to reload the Prescaler and the Repetition counter

     values immediately */

  TIMx->EGR = TIM_PSCReloadMode_Immediate;           

}

只看该作者 · 2024-3-31 14:51

TIM_Cmd

复制

/**

  * @brief  Enables or disables the specified TIM peripheral.

  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.

  * @param  NewState: new state of the TIMx peripheral.

  *   This parameter can be: ENABLE or DISABLE.

  * @retval None

  */

void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)

{

  /* Check the parameters */

  assert_param(IS_TIM_ALL_PERIPH(TIMx));

  assert_param(IS_FUNCTIONAL_STATE(NewState));

  

  if (NewState != DISABLE)

  {

    /* Enable the TIM Counter */

    TIMx->CR1 |= TIM_CR1_CEN;

  }

  else

  {

    /* Disable the TIM Counter */

    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));

  }

}

只看该作者 · 2024-3-31 14:51

TIM_SetCounter
/**
  * @brief  Sets the TIMx Counter Register value
  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
  * @param  Counter: specifies the Counter register new value.
  * @retval None
  */
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
{
  /* Check the parameters */
  assert_param(IS_TIM_ALL_PERIPH(TIMx));
  /* Set the Counter Register value */
  TIMx->CNT = Counter;
}

只看该作者 · 2024-3-31 14:51

TIM_GetCounter

复制

/**

  * @brief  Gets the TIMx Counter value.

  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.

  * @retval Counter Register value.

  */

uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)

{

  /* Check the parameters */

  assert_param(IS_TIM_ALL_PERIPH(TIMx));

  /* Get the Counter Register value */

  return TIMx->CNT;

}

只看该作者 · 2024-3-31 14:51

TIM_ITConfig

/**
  * @brief  Enables or disables the specified TIM interrupts.
  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
  * This parameter can be any combination of the following values:
  *    @ARG TIM_IT_Update: TIM update Interrupt source
  *    @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  *    @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  *    @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  *    @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  *    @arg TIM_IT_COM: TIM Commutation Interrupt source
  *    @arg TIM_IT_Trigger: TIM Trigger Interrupt source
  *    @arg TIM_IT_Break: TIM Break Interrupt source
  * @NOTE
  * - TIM6 and TIM7 can only generate an update interrupt.
  * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
  *    TIM_IT_CC2 or TIM_IT_Trigger.
  * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
  * @param  NewState: new state of the TIM interrupts.
  * This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_TIM_ALL_PERIPH(TIMx));
  assert_param(IS_TIM_IT(TIM_IT));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
/* Enable the Interrupt sources */
TIMx->DIER |= TIM_IT;
  }
  else
  {
/* Disable the Interrupt sources */
TIMx->DIER &= (uint16_t)~TIM_IT;
  }
}

只看该作者 · 2024-3-31 14:51

TIM_ClearITPendingBit
/**
  * @brief  Clears the TIMx's interrupt pending bits.
  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
  * @param  TIM_IT: specifies the pending bit to clear.
  * This parameter can be any combination of the following values:
  *    @arg TIM_IT_Update: TIM1 update Interrupt source
  *    @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  *    @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  *    @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  *    @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  *    @arg TIM_IT_COM: TIM Commutation Interrupt source
  *    @arg TIM_IT_Trigger: TIM Trigger Interrupt source
  *    @arg TIM_IT_Break: TIM Break Interrupt source
  * @note
  * - TIM6 and TIM7 can generate only an update interrupt.
  * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
  *    TIM_IT_CC2 or TIM_IT_Trigger.
  * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
  * @retval None
  */
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
{
  /* Check the parameters */
  assert_param(IS_TIM_ALL_PERIPH(TIMx));
  assert_param(IS_TIM_IT(TIM_IT));
  /* Clear the IT pending Bit */
  TIMx->SR = (uint16_t)~TIM_IT;
}

只看该作者 · 2024-3-31 14:52

TIM_OCInit

void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
  uint16_t tmpccmrx = 0, tmpccer = 0;

  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;
  tmpccer = TIMx->CCER;

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= (uint16_t)(~(uint16_t)(TIM_CCMR1_OC1M | TIM_CCMR1_CC1S));
  tmpccer &= (uint16_t)(~(uint16_t)TIM_CCER_CC1P);

  /* Select the Output Compare Mode */
  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 4);

  /* Select the Output Polarity */
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 1);

  /* Set the Capture Compare Register value */
  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer | (uint16_t)TIM_CCER_CC1E;
}

只看该作者 · 2024-3-31 14:52

TIM_OCxInit
TIM_OC1Init
/**
  * @brief  Initializes the TIMx Channel1 according to the specified
  *       parameters in the TIM_OCInitStruct.
  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
  *       that contains the configuration information for the specified TIM peripheral.
  * @retval None
  */
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

  /* Check the parameters */
  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));

  /* Select the Output Compare Mode */
  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;

  /* Reset the Output Polarity level */
  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
  /* Set the Output Compare Polarity */
  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;

  /* Set the Output State */
  tmpccer |= TIM_OCInitStruct->TIM_OutputState;

  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
   (TIMx == TIM16)|| (TIMx == TIM17))
  {
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));

/* Reset the Output N Polarity level */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
/* Set the Output N Polarity */
tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;

/* Reset the Output N State */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
/* Set the Output N State */
tmpccer |= TIM_OCInitStruct->TIM_OutputNState;

/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));

/* Set the Output Idle state */
tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
/* Set the Output N Idle state */
tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
  }
  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

只看该作者 · 2024-3-31 14:52

TIM_OC2Init
/**
  * @brief  Initializes the TIMx Channel2 according to the specified
  *       parameters in the TIM_OCInitStruct.
  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
  *       the TIM peripheral.
  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
  *       that contains the configuration information for the specified TIM peripheral.
  * @retval None
  */
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

  /* Check the parameters */
  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));

  /* Select the Output Compare Mode */
  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);

  /* Reset the Output Polarity level */
  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
  /* Set the Output Compare Polarity */
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);

  /* Set the Output State */
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);

  if((TIMx == TIM1) || (TIMx == TIM8))
  {
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));

/* Reset the Output N Polarity level */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
/* Set the Output N Polarity */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);

/* Reset the Output N State */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
/* Set the Output N State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);

/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));

/* Set the Output Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
/* Set the Output N Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
  }
  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

只看该作者 · 2024-3-31 14:53

TIM_OC3Init
/**
  * @brief  Initializes the TIMx Channel3 according to the specified
  *       parameters in the TIM_OCInitStruct.
  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
  *       that contains the configuration information for the specified TIM peripheral.
  * @retval None
  */
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
  /* Select the Output Compare Mode */
  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;

  /* Reset the Output Polarity level */
  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
  /* Set the Output Compare Polarity */
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);

  /* Set the Output State */
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);

  if((TIMx == TIM1) || (TIMx == TIM8))
  {
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));

/* Reset the Output N Polarity level */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
/* Set the Output N Polarity */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
/* Reset the Output N State */
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));

/* Set the Output N State */
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
/* Set the Output Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
/* Set the Output N Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
  }
  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

只看该作者 · 2024-3-31 14:55

TIM_OC4Init
/**
  * @brief  Initializes the TIMx Channel4 according to the specified
  *       parameters in the TIM_OCInitStruct.
  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
  *       that contains the configuration information for the specified TIM peripheral.
  * @retval None
  */
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
  /* Disable the Channel 2: Reset the CC4E Bit */
  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));

  /* Select the Output Compare Mode */
  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);

  /* Reset the Output Polarity level */
  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
  /* Set the Output Compare Polarity */
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);

  /* Set the Output State */
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);

  if((TIMx == TIM1) || (TIMx == TIM8))
  {
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
/* Set the Output Idle state */
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
  }
  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

只看该作者 · 2024-3-31 14:55

TIM_SetComparex
TIM_SetCompare1
/**
  * @brief  Sets the TIMx Capture Compare1 Register value
  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
  * @param  Compare1: specifies the Capture Compare1 register new value.
  * @retval None
  */
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
{
  /* Check the parameters */
  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
  /* Set the Capture Compare1 Register value */
  TIMx->CCR1 = Compare1;
}

只看该作者 · 2024-3-31 14:55

TIM_SetCompare2
/**
  * @brief  Sets the TIMx Capture Compare2 Register value
  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
  * @param  Compare2: specifies the Capture Compare2 register new value.
  * @retval None
  */
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
{
  /* Check the parameters */
  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
  /* Set the Capture Compare2 Register value */
  TIMx->CCR2 = Compare2;
}

只看该作者 · 2024-3-31 15:01

TIM_SetCompare3
/**
  * @brief  Sets the TIMx Capture Compare3 Register value
  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  Compare3: specifies the Capture Compare3 register new value.
  * @retval None
  */
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
{
  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  /* Set the Capture Compare3 Register value */
  TIMx->CCR3 = Compare3;
}

只看该作者 · 2024-3-31 15:01

TIM_SetCompare4
/**
  * @brief  Sets the TIMx Capture Compare4 Register value
  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  Compare4: specifies the Capture Compare4 register new value.
  * @retval None
  */
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
{
  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  /* Set the Capture Compare4 Register value */
  TIMx->CCR4 = Compare4;
}

只看该作者 · 2024-3-31 15:02

TIM_PWMOutputState
void TIM_PWMOutputState(TIM_TypeDef* TIMx, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
/* Enable the TIM Main Output */
TIMx->BDTR |= TIM_BDTR_MOE;
  }
  else
  {
/* Disable the TIM Main Output */
TIMx->BDTR &= (uint16_t)~((uint16_t)TIM_BDTR_MOE);
  }
}

只看该作者 · 2024-3-31 15:02

TIM_CtrlPWMOutputs
/**
  * @brief  Enables or disables the TIM peripheral Main Outputs.
  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
  * @param  NewState: new state of the TIM peripheral Main Outputs.
  * This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  {
/* Enable the TIM Main Output */
TIMx->BDTR |= TIM_BDTR_MOE;
  }
  else
  {
/* Disable the TIM Main Output */
TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
  }
}

只看该作者 · 2024-3-31 15:02

TIM_ETRClockMode2Config
/**
  * @brief  Configures the External clock Mode2
  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
  * This parameter can be one of the following values:
  *    @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  *    @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  *    @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  *    @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
  * This parameter can be one of the following values:
  *    @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  *    @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
  * @param  ExtTRGFilter: External Trigger Filter.
  * This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
                           uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
{
  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
  /* Configure the ETR Clock source */
  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
  /* Enable the External clock mode2 */
  TIMx->SMCR |= TIM_SMCR_ECE;
}