| GPIO_InitTypeDef GPIO_InitStruct; DMA_InitTypeDef DMA_InitStructure;
 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
 TIM_OCInitTypeDef  TIM_OCInitStructure;
 
 uint16_t TimerPeriod = 0;
 
 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
 
 /* GPIOA Configuration: Channel 2 as alternate function push-pull */
 GPIO_InitStruct.GPIO_Pin =  GPIO_Pin_6;
 GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
 GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
 GPIO_Init(GPIOB, &GPIO_InitStruct);
 
 /* DMA1 Channel5 Config */
 DMA_DeInit(DMA1_Channel1);
 
 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM4_CCR1_Address;
 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
 DMA_InitStructure.DMA_BufferSize = 3;
 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
 DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
 
 DMA_Init(DMA1_Channel1, &DMA_InitStructure);
 
 /* DMA1 Channel5 enable */
 DMA_Cmd(DMA1_Channel1, ENABLE);
 
 /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
 TimerPeriod = (SystemCoreClock / 1000 ) - 1;
 /* Compute CCR1 value to generate a duty cycle at 50% */
 SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
 /* Compute CCR1 value to generate a duty cycle at 37.5% */
 SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
 /* Compute CCR1 value to generate a duty cycle at 25% */
 SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
 
 /* TIM4 Peripheral Configuration --------------------------------------------*/
 /* Time Base configuration */
 TIM_TimeBaseStructure.TIM_Prescaler = 0;
 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
 TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
 TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
 
 /* Channel 2 Configuration in PWM mode */
 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
 //        TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
 TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0];
 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
 //        TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
 TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
 //        TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
 
 TIM_OC1Init(TIM4, &TIM_OCInitStructure);
 
 /* TIM4 Update DMA Request enable */
 TIM_DMACmd(TIM4, TIM_DMA_CC1, ENABLE);
 
 //        TIM_CCPreloadControl(TIM4, ENABLE);
 
 /* TIM1 counter enable */
 TIM_Cmd(TIM4, ENABLE);
 
 /* Main Output Enable */
 TIM_CtrlPWMOutputs(TIM4, ENABLE);
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