用MAX7064实现PCI本地总线接口，源代码如下：

只看该作者 · 2012-7-10 14:23

用MAX7064实现PCI本地总线接口，大家帮忙看看我的程序是否有问题？

module PCI_TTL_IO_Card(
               sys_rst_n,
   int_clk,
   DQ2, DQ3,
               ADCLK, PTATN, PTADR, PTWR, DXFR, PTBE,

               CLK_LATCH, CLK_LATCH7, OE_READ,OE_READ7,
   add_int
               );
input sys_rst_n;
input DQ2;
input DQ3;
input ADCLK;
input PTATN;
input PTADR;
input PTWR;
input DXFR;
input [3:0] PTBE;
input int_clk;
output add_int;
output [3:0] CLK_LATCH;
output [3:0] OE_READ;
output OE_READ7;
output CLK_LATCH7;
reg [3:0] PTBE_REG;
reg [3:0] CLK_LATCH_REG;
reg [3:0] OE_READ_REG;
reg [4:0] count;
reg add_int_reg;
reg [1:0] DQ;
reg [1:0] PTADDR;
reg [1:0] DXFR_CNT;
reg [1:0] DXFR_CNT_REG;
reg CLK_LATCH7_REG;
reg OE_READ7_REG;

//Clear DXFR_CNT at the begin of every data transaction or system reset
always @ ( negedge ADCLK ) //or negedge sys_rst_n
begin
      if(!PTATN)
      DXFR_CNT_REG = 2'b00;
end

//lock up the ADDRESS
always @ ( negedge ADCLK )  //
begin
      if( !PTADR)
      DQ <= {DQ3, DQ2};
end

//issue READ or WRITE signals
always @ ( negedge ADCLK or negedge sys_rst_n) //negedge DXFR or
if(! sys_rst_n)
      begin
         CLK_LATCH_REG <= 4'b0000;
         OE_READ_REG <= 4'b1111;
   end

  else if (!DXFR)
begin
   PTBE_REG = PTBE;  //get the current Byte Enable bits
      PTADDR = DQ;
DXFR_CNT = DXFR_CNT_REG;

   if(PTADDR == 2'b10)
      begin
      if(  PTWR  )
                  CLK_LATCH_REG <= ~PTBE_REG;

            else if( !PTWR )
                  OE_READ_REG <= PTBE_REG;

            else
                  begin
                     CLK_LATCH_REG <= 4'b0000;
                     OE_READ_REG <= 4'b1111;
                  end
end
      else if (PTADDR == 2'b11)
   begin
      if((DXFR_CNT == 2'b11) && PTWR)
      CLK_LATCH7_REG <= 1'b1;

   else if((DXFR_CNT == 2'b11) && (!PTWR))
      OE_READ7_REG <= 1'b0;
end

DXFR_CNT <= DXFR_CNT + 1'b1;

end
else if(DXFR)
      begin
      CLK_LATCH7_REG <= 1'b0;
      OE_READ7_REG <= 1'b1;
end


//issue 15.625KHz INT signal
always @ (posedge int_clk or negedge sys_rst_n)
begin
      if(! sys_rst_n)
      count <= 5'b00000;
      else
         begin
            count <= count + 1'b1;
            if(count == 5'b11111)       //32 divider
               begin
                  add_int_reg <= 1'b0;
                  count    <= 5'h0;    //
               end
            else
               add_int_reg <= 1'b1;
         end
end
assign add_int = add_int_reg;

assign CLK_LATCH  = CLK_LATCH_REG;
assign OE_READ = OE_READ_REG;
assign OE_READ7 = OE_READ7_REG;
assign CLK_LATCH7 = CLK_LATCH7_REG;
endmodule