/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanaShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP280x_Examples.h
/* The following block for all 100 MHz SYSCLKOUT - default. Bit rate = 1 Mbps */
// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
发送的语句
ECanaRegs.CANMC.bit.CDR = 1; // Set the change data request bit
ECanaMboxes.MBOX0.MDL.all = aver_ADCB0_vol;
ECanaShadow.CANTRS.all =0;
ECanaShadow.CANTRS.bit.TRS1 = 1; // Set TRS for all transmit mailboxes
ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;
while(ECanbRegs.CANTA.bit.TA1 == 0 ) {} // Wait for all TAn bits to be set..
ECanaShadow.CANTA.all = 0x00000000;
ECanaShadow.CANTA.bit.TA1 = 1; // Clear all TAn
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
// Configure the eCAN for self test mode
// Enable the enhanced features of the eCAN.
EALLOW;
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.STM = 0; // Configure CAN for self-test mode
ECanbShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
EDIS;
// Write to the MSGID field of RECEIVE mailboxes MBOX16
ECanbMboxes.MBOX16.MSGID.all = 0x9555AAA0;
/* // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanbRegs.CANMD.all = 0xFFFF0000;
*/
//ÓÊÏä0ΪTX
ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
ECanbShadow.CANMD.bit.MD0 =0;
ECanbShadow.CANMD.bit.MD16 =1;
ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;
/* // Enable all Mailboxes
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanbRegs.CANME.all = 0xFFFFFFFF;
*/
// Specify that 8 bits will be sent/received
ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
// No remote frame is requested ûÓÐÔ¶·½Ó¦´ðÖ¡
// Since RTR bit is undefined upon reset,
// it must be initialized to the proper value
ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0;
// Write to the mailbox RAM field of MBOX0
ECanbMboxes.MBOX0.MDL.all = 0x01010101;
ECanbMboxes.MBOX0.MDH.all = 0x01010101;
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
EALLOW;
ECanbRegs.CANMIM.all = 0xFFFFFFFF;//ʹÄÜÓÊÏäÖжÏ
// Request permission to change the configuration registers
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.CCR = 1;
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
EDIS;
// Wait until the CPU has been granted permission to change the
// configuration registers
// Wait for CCE bit to be set..
do
{
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
} while(ECanbShadow.CANES.bit.CCE != 1 );
// Configure the eCAN timing
EALLOW;
ECanbShadow.CANBTC.all = ECanbRegs.CANBTC.all;
ECanbShadow.CANBTC.bit.BRPREG = 9; // (BRPREG + 1) = 10 feeds a 15 MHz CAN clock
ECanbShadow.CANBTC.bit.TSEG2REG = 5 ; // to the CAN module. (150 / 10 = 15) 5 7
ECanbShadow.CANBTC.bit.TSEG1REG = 7; // Bit time = 15 7 15
ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;//1Mbps 600
// Wait until the CPU no longer has permission to change the
// configuration registers
do
{
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
} while(ECanbShadow.CANES.bit.CCE != 0 );
ECanbRegs.CANTRS.all = 0x00000001; // Set TRS for all transmit mailboxes
// while(ECanbRegs.CANTA.all == 0x0000FFFF ) {} // Wait for all TAn bits to be set..
while(ECanbRegs.CANTA.all == 0){}
ECanbRegs.CANTA.all = 0x00000001; // Clear Mailbox0 TAn
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