PIE中断可以支持96个独立中断，这些中断分为8个小组，每个小组包含12个中断。
CPU经过9个时钟周期获取中断向量地址和保存关键寄存器数据之后才能执行中断程序。
28335在CPU级支持一个不可屏蔽中断（NMI）和16个可屏蔽中断（INT1-INT14，RTOSINT,DLOGINT）。
PIE的用处：
The PIE vector table is used to store the address (vector) of each interrupt service routine (ISR) within the
system.
PIE中断的作用机理：
1PeripheralLevel
An interrupt-generating event occurs in a peripheral. The interrupt flag (IF) bit corresponding to that
event is set in a register for that particular peripheral.
If the corresponding interrupt enable (IE) bit is set, the peripheral generates an interrupt request to the
PIE controller. If the interrupt is not enabled at the peripheral level, then the IF remains set until
cleared by software. If the interrupt is enabled at a later time, and the interrupt flag is still set, the
interrupt request is asserted to the PIE.
Interrupt flags within the peripheral registers must be manually cleared. See the peripheral reference
guide for a specific peripheral for more information.
2 PIE级别
PIE模块汇集8个外设和管脚中断进入一个CPU中断
PIE group1 ----group12分别对应了CPU中断1---中断12
对于不可屏蔽中断来说，它直接进入CPU级。
对于可屏蔽中断来说，PIE模块有相关的标志寄存器(PIEIFRx和PIEIERx)(x=1-------12)每一个位设为y(y=1-----8)
PIEIERx.y 和PIEIFRx.y，
除此之外，对于每一个PIE中断组来说(1----12)还有一个PIE响应标志位PIEACK，如PIEACKx(x=1----12)
机理如下：当有中断请求进入PIE控制器的时候，相关的PIE中断标志位PIEIFRx.y置高。如果PIE中断允许位PIEIERx.y也置高的时候，PIE控制器机会检查PIEACKx标志位来决定CPU是否已经准备好接收这个PIE中断组的中断。
如果PIEACKZx被清零了，那么PIE会把这个中断请求送到CPU级。
如果PIEACKx位置一，那么PIE就会等待直到这个标志位清零然后发送中断请求给CPU级的INTx。（TMS320F2833X SYSTEM CONTROL AND INTERRUPTS REFERENCE GUIDE）
3 CPU级
一旦中断请求到达CPU级，CPU级和INTx相对应的中断标志位(IFR)置一，如果CPU中断允许寄存器(IER)或者调试中断允许寄存器(DBGIER)和全局中断屏蔽位(INTM)允许的话，CPU才会执行这个中断申请。
中断过程中需要手动清零的寄存器：
PIEACKx 写1 清零
PIE中断寄存器
1 PIECTRL
BITS15-1:PIEVECT 中断向量表的地址(指向中断程序)
BIT0:ENPIE =1允许从中断向量表中获取中断程序入口地址
2 PIEACK
bit0~bit11 refers to PIE group 1~12
3 PIEIFRx
bit0~7 refers to INTx.1~INTx.8
4 PIEIERx
bit0~7 refers to INTx.1~INTx.8 1：使能 0：禁能
CPU中断寄存器
1 IFR
2 IER
3 XINTnCR 外部中断控制寄存器（支持XINT1~XINT7，n=1~7。XINT13和不可屏蔽中断XNMI多路复用）
BIT3 BIT2
00 Interrupt generated on a falling edge (high-to-low transition)
01 Interrupt generated on a rising edge (low-to-high transition)
10 Interrupt is generated on a falling edge (high-to-low transition)
11 Interrupt generated on both a falling edge and a rising edge (high-to-low and low-to-high transition)
BIT0 ENABLE 0 禁止中断 1 使能中断
4 XNMICR 外部NMI中断控制寄存器
BIT3 BIT2
00 Interrupt generated on a falling edge (high-to-low transition)
01 Interrupt generated on a rising edge (low-to-high transition)
10 Interrupt is generated on a falling edge (high-to-low transition)
11 Interrupt generated on both a falling edge and a rising edge (high-to-low and low-to-high transition)
BIT1 0-----INT13用于定时器1 中断 1----INT13用于XNMI_XINT13中断
BIT0 ENABLE 0 禁止中断 1 使能中断 |
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