在进行MCB读写DDR2仿真时，calib_done一直为低电平。调试：对自己写的读写控制模块进行仿真时，calib_done一直为低电平。看了波形，感觉像是MCB里的infrastructure模块的PLL_ADV产生时钟没有振起来。我用IP core生成该MCB的user_design里头的sim.do文件仿真，功能正确。这说明MCB模块里头文件应该没问题吧。也就是问题可能出现在我的读写控制模块，或者testbench？但是下载到板子读写（固定数据写入读出）能够实现，就不知道数据是否完全正确。望大牛指点一二，万分感谢。。。。
附上：testbench
`timescale 1ps/1ps
module tb_sdram;
parameter DEBUG_EN = 0;
localparam DBG_WR_STS_WIDTH = 32;
localparam DBG_RD_STS_WIDTH = 32;
localparam C3_P0_PORT_MODE = "BI_MODE";
localparam C3_P1_PORT_MODE = "NONE";
localparam C3_P2_PORT_MODE = "NONE";
localparam C3_P3_PORT_MODE = "NONE";
localparam C3_P4_PORT_MODE = "NONE";
localparam C3_P5_PORT_MODE = "NONE";
localparam C3_PORT_ENABLE = 6'b000001;
localparam C3_PORT_CONFIG = "B32_B32_R32_R32_R32_R32";
parameter C3_MEMCLK_PERIOD = 3200;
parameter C3_RST_ACT_LOW = 0;
parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C3_NUM_DQ_PINS = 16;
parameter C3_MEM_ADDR_WIDTH = 13;
parameter C3_MEM_BANKADDR_WIDTH = 3;
parameter C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
parameter C3_P0_MASK_SIZE = 4;
parameter C3_P0_DATA_PORT_SIZE = 32;
parameter C3_P1_MASK_SIZE = 4;
parameter C3_P1_DATA_PORT_SIZE = 32;
parameter C3_MEM_BURST_LEN = 4;
parameter C3_MEM_NUM_COL_BITS = 10;
parameter C3_CALIB_SOFT_IP = "TRUE";
parameter C3_SIMULATION = "TRUE";
//parameter C3_HW_TESTING = "FALSE"; // Inputs
reg c3_sys_clk;
wire c3_sys_rst_i; // Outputs
wire [12:0] mcb3_dram_a;
wire [2:0] mcb3_dram_ba;
wire mcb3_dram_ras_n;
wire mcb3_dram_cas_n;
wire mcb3_dram_we_n;
wire mcb3_dram_odt;
wire mcb3_dram_cke;
wire mcb3_dram_dm;
wire mcb3_dram_udm;
wire mcb3_dram_ck;
wire mcb3_dram_ck_n; // Bidirs
wire [15:0] mcb3_dram_dq;
wire mcb3_dram_udqs;
wire mcb3_dram_udqs_n;
wire mcb3_rzq;
wire mcb3_zio;
wire mcb3_dram_dqs;
wire mcb3_dram_dqs_n; wire calib_done;
// Instantiate the Unit Under Test (UUT)
atlys_mcb_demo #(.C3_P0_MASK_SIZE (C3_P0_MASK_SIZE ),
.C3_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE ),
.C3_P1_MASK_SIZE (C3_P1_MASK_SIZE ),
.C3_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE ),
.C3_MEMCLK_PERIOD (C3_MEMCLK_PERIOD),
.C3_RST_ACT_LOW (C3_RST_ACT_LOW),
.C3_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE),
.DEBUG_EN (DEBUG_EN),.C3_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER ),
.C3_NUM_DQ_PINS (C3_NUM_DQ_PINS ),
.C3_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH ),
.C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),//.C3_HW_TESTING (C3_HW_TESTING),
.C3_SIMULATION (C3_SIMULATION),
.C3_CALIB_SOFT_IP (C3_CALIB_SOFT_IP )
)
uut (
.mcb3_dram_dq(mcb3_dram_dq),
.mcb3_dram_a(mcb3_dram_a),
.mcb3_dram_ba(mcb3_dram_ba),
.calib_done(calib_done),
.mcb3_dram_ras_n(mcb3_dram_ras_n),
.mcb3_dram_cas_n(mcb3_dram_cas_n),
.mcb3_dram_we_n(mcb3_dram_we_n),
.mcb3_dram_odt(mcb3_dram_odt),
.mcb3_dram_cke(mcb3_dram_cke),
.mcb3_dram_dm(mcb3_dram_dm),
.mcb3_dram_udqs(mcb3_dram_udqs),
.mcb3_dram_udqs_n(mcb3_dram_udqs_n),
.mcb3_rzq(mcb3_rzq),
.mcb3_zio(mcb3_zio),
.mcb3_dram_udm(mcb3_dram_udm),
.c3_sys_clk(c3_sys_clk),
.c3_sys_rst_i(c3_sys_rst_i),
.mcb3_dram_dqs(mcb3_dram_dqs),
.mcb3_dram_dqs_n(mcb3_dram_dqs_n),
.mcb3_dram_ck(mcb3_dram_ck),
.mcb3_dram_ck_n(mcb3_dram_ck_n)
);
generate
if(C3_NUM_DQ_PINS == 16) begin : MEM_INST3
ddr2_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_rdqs ({mcb3_dram_udm,mcb3_dram_dm}),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs ({mcb3_dram_udqs,mcb3_dram_dqs}),
.dqs_n ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
.rdqs_n (),
.odt (mcb3_dram_odt)
);
end else begin
ddr2_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_rdqs (mcb3_dram_dm),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs (mcb3_dram_dqs),
.dqs_n (mcb3_dram_dqs_n),
.rdqs_n (),
.odt (mcb3_dram_odt)
);
end
endgenerate
PULLDOWN zio_pulldown3 (.O(mcb3_rzq));
PULLDOWN rzq_pulldown3 (.O(mcb3_zio));
initial begin
// Initialize Inputs
c3_sys_clk = 0;
end
reg c3_sys_rst;
initial begin
c3_sys_rst = 1'b0;
#20000;
c3_sys_rst = 1'b1;
end
assign c3_sys_rst_i = C3_RST_ACT_LOW ? c3_sys_rst : ~c3_sys_rst;
always #5 c3_sys_clk = !c3_sys_clk;// ========================================================================== //
// Reporting the test case status
// ========================================================================== //
initial
begin : Logging
fork
begin : calibration_done
wait (calib_done);
$display("Calibration Done");
#50000000;
$display("TEST DONE");
disable calib_not_done;
$finish;
end
begin : calib_not_done
#200000000;
if (!calib_done) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end endmodule |
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