用VHDL写的程序如下，仿真波形也出来了，硬件没有反应。求解答。。。
我的想法是，先送时钟，再送数据，将16位数sdi，从高位到低位逐个输出到sdo，但是不行？
有三个进程，一个是状态转换，一个是输出，一个是锁存（对于输出信号q锁存输出，这个是测试信号，可以不管），新手求解答。。
library ieee;
use ieee.std_logic_1164.all;
entity coms595 is
port
(
clk : in std_logic; --基本时钟，关乎于状态的转换和sclk的转换
sdi : in std_logic_vector(15 downto 0); --连接到ram或者rom
q : out std_logic_vector(15 downto 0); --可以连接到8位输出接口，例如LED灯
sdo : out std_logic; --连接到595的串行输入sdi端
sclk : out std_logic; --连接到595的SHIFT CLOCK
pclk : out std_logic; --连接到595的LATCH CLOCK
oe : out std_logic --连接到595的OE端
);
end coms595;
architecture behav of coms595 is
type states is(s,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,s32);
signal cs,next_state : states:=s;
signal q_temp : std_logic_vector(15 downto 0);
signal lock : std_logic; --锁存输出的时钟
begin
reg : process(cs,clk) --主控时序进程
begin
if clk'event and clk='1' then
cs<=next_state;
end if;
end process reg;
com1:process(cs)
begin
case cs is
when s=> next_state<=s0;
when s0 => next_state<=s1;
when s1 => next_state<=s2;
when s2 => next_state<=s3;
when s3 => next_state<=s4;
when s4 => next_state<=s5;
when s5 => next_state<=s6;
when s6 => next_state<=s7;
when s7 => next_state<=s8;
when s8 => next_state<=s9;
when s9 => next_state<=s10;
when s10 => next_state<=s11;
when s11 => next_state<=s12;
when s12 => next_state<=s13;
when s13 => next_state<=s14;
when s14 => next_state<=s15;
when s15 => next_state<=s16;
when s16 => next_state<=s17;
when s17 => next_state<=s18;
when s18 => next_state<=s19;
when s19 => next_state<=s20;
when s20 => next_state<=s21;
when s21 => next_state<=s22;
when s22 => next_state<=s23;
when s23 => next_state<=s24;
when s24 => next_state<=s25;
when s25 => next_state<=s26;
when s26 => next_state<=s27;
when s27 => next_state<=s28;
when s28 => next_state<=s29;
when s29 => next_state<=s30;
when s30 => next_state<=s31;
when s31 => next_state<=s32;
when s32 => next_state<=s;
when others => next_state<=s;
end case;
end process com1;
com2:process(cs)
begin
case cs is
when s => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(15)<=sdi(15);sdo<=sdi(15);
when s0 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(15)<=sdi(15);sdo<=sdi(15);
when s1 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s2 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(14)<=sdi(14);sdo<=sdi(14);
when s3 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s4 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(13)<=sdi(13);sdo<=sdi(13);
when s5 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s6 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(12)<=sdi(12);sdo<=sdi(12);
when s7 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s8 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(11)<=sdi(11);sdo<=sdi(11);
when s9 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s10 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(10)<=sdi(10);sdo<=sdi(10);
when s11 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s12 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(9)<=sdi(9);sdo<=sdi(9);
when s13 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s14 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(8)<=sdi(8);sdo<=sdi(8);
when s15 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s16 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(7)<=sdi(7);sdo<=sdi(7);
when s17 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s18 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(6)<=sdi(6);sdo<=sdi(6);
when s19 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s20 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(5)<=sdi(5);sdo<=sdi(5);
when s21 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s22 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(4)<=sdi(4);sdo<=sdi(4);
when s23 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s24 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(3)<=sdi(3);sdo<=sdi(3);
when s25 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s26 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(2)<=sdi(2);sdo<=sdi(2);
when s27 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s28 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(1)<=sdi(1);sdo<=sdi(1);
when s29 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s30 => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(0)<=sdi(0);sdo<=sdi(0);
when s31 => sclk<='1';pclk<='0';oe<='0';lock<='0';
when s32 => sclk<='0';pclk<='1';oe<='0';lock<='1';
when others => sclk<='0';pclk<='0';oe<='0';lock<='0';q_temp(15)<=sdi(15);sdo<=sdi(15);
end case;
end process com2;
latch:process(lock)
begin
if lock'event and lock='1' then
q<=q_temp;
end if;
end process latch;
end behav;
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