library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ram is
generic(width:integer :=8;length:integer:=256);
port(clk:in std_logic;
r_add,w_add:in std_logic_vector(7 downto 0);
restart,r_en,w_en:in std_logic;
d_in:in std_logic_vector(width-1 downto 0);
d_out:out std_logic_vector(width-1 downto 0));
end entity;
architecture art of ram is
type memory is array (0 to length-1) of std_logic_vector(width-1 downto 0);
signal data:memory;
begin
process(clk,w_add,w_en,d_in)
begin
if clk'event and clk='1' then
if w_en='1' then
data(conv_integer(w_add))<=d_in;
end if;
end if;
end process;
process(clk,r_add,r_en,data)
begin
if clk'event and clk='1' then
if r_en='1' then
d_out<=data(conv_integer(r_add));
end if;
end if;
end process;
end art;
|
楼主
