# Reading C:/altera/10.0/modelsim_ase/tcl/vsim/pref.tcl
# do vga_nios_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying C:\altera\10.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:\altera\10.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
#
# vlog -vlog01compat -work work +incdir+D:/nios_project/vga {D:/nios_project/vga/vga_controller_stream.v}
# Model Technology ModelSim ALTERA vlog 6.5e Compiler 2010.02 Feb 27 2010
# -- Compiling module vga_controller_stream
#
# Top level modules:
# vga_controller_stream
# vcom -93 -work work {D:/nios_project/vga/VGA_Timing.vhd}
# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity vga_timing
# -- Compiling architecture translated of vga_timing
# vcom -93 -work work {D:/nios_project/vga/vga_pixel_fifo.vhd}
# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity vga_pixel_fifo
# -- Compiling architecture syn of vga_pixel_fifo
#
# vcom -93 -work work {D:/nios_project/vga/simulation/modelsim/vga_testbench.vhd}
# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity vga_testbench
# -- Compiling architecture behavior of vga_testbench
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L cyclone -L rtl_work -L work -voptargs="+acc" vga_testbench
# vsim -L altera -L lpm -L sgate -L altera_mf -L cyclone -L rtl_work -L work -voptargs=\"+acc\" -t 1ps vga_testbench
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading ieee.numeric_std(body)
# Loading work.vga_testbench(behavior)
# ALTERA version supports only a single HDL
# ** Error: (vsim-3039) D:/nios_project/vga/simulation/modelsim/vga_testbench.vhd(40): Instantiation of 'vga_controller_stream' failed.
# Region: /vga_testbench
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./vga_nios_run_msim_rtl_vhdl.do PAUSED at line 14 |
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