LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY SEVEN IS PORT (clk : IN STD_LOGIC; rst : IN STD_LOGIC; clk_out : OUT STD_LOGIC);END ENTITY;ARCHITECTURE behav OF SEVEN IS SIGNAL temp : STD_LOGIC;SIGNAL temp1,temp2 : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN p1:PROCESS(clk,rst) BEGIN IF(clk'event AND clk='1')THEN IF(rst='1')THEN clk_out<='0'; ELSE CASE temp1 IS WHEN "000" => temp1<="001"; WHEN "001" => temp1<="010"; WHEN "010" => temp1<="011"; WHEN "011" => temp1<="100"; WHEN "100" => temp1<="101"; WHEN "101" => temp1<="110"; WHEN "110" => temp1<="000"; WHEN OTHERS => temp1<="000"; END CASE; END IF; END IF; IF(clk'event AND clk='0')THEN IF(rst='1')THEN clk_out<='0'; ELSE CASE temp2 IS WHEN "000" => temp2<="001"; WHEN "001" => temp2<="010"; WHEN "010" => temp2<="011"; WHEN "011" => temp2<="100"; WHEN "100" => temp2<="101"; WHEN "101" => temp2<="110"; WHEN "110" => temp2<="000"; WHEN OTHERS => temp2<="000"; END CASE; END IF; END IF; clk_out <= NOT (temp1(1) OR temp2(1));END PROCESS;END ARCHITECTURE; 产生1HZlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity ffpin is port (clk1k:in std_logic; ft:out std_logic);end ffpin;architecture a of ffpin issignal fm:std_logic;beginprocess(clk1k)variable num:integer range 0 to 1000;beginif clk1k'event and clk1k='1' then if num<500 then num:=num+1; else num:=1; fm<=not fm; end if ;end if;ft<=fm;end process;能实现吗？ 第二段程序还有点错误
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