在CS4330 datasheet 里关于复位有这么一段话： The device will remain in the PowerDown mode until MCLK and LRCK are presented. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequencyratio. Power is then applied to the internal voltage reference and the +5 or +3 Volt power supply mode is determined. Finally, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will move to approximately 2.3V (1.3V in 3V mode). This process requires approximately 1ms plus 1024 cycles of LRCK. 大体意思是CS4330在上电复位后，自动检测过采样比MCLK/LRCK要花费大约1ms＋1024个Ts（采样周期），在最低MP3采样频率16KHz条件下，延迟时间是65ms，人耳朵可能听不到。
在CS4334的datasheet里又有关于复位的表述： When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. After a short delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent voltage, VQ. Approximately 10,000 sample cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to VQ, effectively blocking the quiescent DC voltage. 从上电复位到有输出要延迟更长时间。16KHz采样频率条件下，大约1秒左右。
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