VHDL 编写 testbench

只看该作者 · 2013-1-23 15:26

本帖最后由 cuianbin 于 2013-1-23 15:30 编辑

最近在用DSPbuilder  想对生成的VHDL 代码进行Modelsim仿真，无奈以前用的是Verilog 现在转到VHDL 上来有些不适应，关于Testbench 的问题请教大家：
LIBRARY ieee  ;
USE ieee.numeric_std.all  ;
USE ieee.std_logic_1164.all  ;
ENTITY sinwave_gn_tb  IS
END ;

ARCHITECTURE sinwave_gn_tb_arch OF sinwave_gn_tb IS
COMPONENT sinwave_gn
PORT (
   clock  : in std_logic ;
   output  : out std_logic_vector (7 downto 0) ;
   aclr  : in std_logic ;
   sinctrl  : in std_logic );
  END COMPONENT ;

  SIGNAL clock :  std_logic := '0'  ;
  SIGNAL output :  std_logic_vector (7 downto 0)  ;
  SIGNAL aclr :  std_logic := '0'  ;
  SIGNAL sinctrl :  std_logic := '0'  ;
constant clk_period: TIME:=50ns;
BEGIN
  DUT  : sinwave_gn
PORT MAP (
   clock => clock  ,
   output => output  ,
   aclr => aclr  ,
   sinctrl => sinctrl ) ;


   ClockProcess: process
   begin
   clock<='0';
   wait for clk_period/2;
   clock<='1';
   wait for clk_period/2;
   end process ClockProcess;

simProcess: process
   begin
   aclr<='1';
   sinctrl<='1' ;
   wait for 50ns;
   aclr<='0';
   wait for 1000ns;
   aclr<='0';
   end process simProcess;

END sinwave_gn_tb_arch;
老是有警告：an abstract literal and an identifier  must have a separater between them