entity ad_pwm is
Port (
FPGA_CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
CS_MFC : in STD_LOGIC;
RD : in STD_LOGIC;
WR : in STD_LOGIC;
A1_5 : in STD_LOGIC_VECTOR (5 downto 1);
D0_15 : inout STD_LOGIC_VECTOR (15 downto 0);
------------
ads7862_for_clk: out std_logic;
ADC_CONV: out std_logic ;
ADC_CS: out std_logic ;
ADC_RD: out std_logic ;
ADC_A0: out std_logic ;
ADC_DATA: in std_logic_vector(11 downto 0);
------------
dir: out std_logic;
ah: out std_logic;
al: out std_logic;
bh: out std_logic;
bl: out std_logic;
ch: out std_logic;
cl: out std_logic
);
end ad_pwm;
-----INTERFACE-------
A1_5_TEMP<=A1_5 & '0';
PROCESS(FPGA_CLK,RESET,CS_MFC)
BEGIN
IF RESET='0' THEN
-- D0_15_TEMP<=(OTHERS=>'0');
ADC_START<='1';
ELSIF RISING_EDGE(FPGA_CLK) THEN
IF CS_MFC='0' THEN
IF RD='0' AND WR='1' THEN
CASE A1_5_TEMP IS
WHEN "001000" => D0_15(11 DOWNTO 0)<=ADC_CHA0_DATA;
WHEN "001010" => D0_15(11 DOWNTO 0)<=ADC_CHA1_DATA;
WHEN "001100" => D0_15(11 DOWNTO 0)<=ADC_CHB0_DATA;
WHEN "001110" => D0_15(11 DOWNTO 0)<=ADC_CHB1_DATA;
WHEN OTHERS => null;
END CASE;
ELSIF RD='1' AND WR='0' THEN
CASE A1_5_TEMP IS
WHEN "100000" => DEAD_DATA<=D0_15(7 downto 0);
WHEN "100010" => PW_CH0_DATA<=D0_15;
WHEN "100100" => PW_CH1_DATA<=D0_15;
WHEN "100110" => PW_CH2_DATA<=D0_15;
WHEN "101000" => PT_DATA<=D0_15;
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END IF;
观察RTL，发现D0_15（11 downtown 0）只为输出口，D0_15(15 DOWNTO 12)只为输入口。怎么不是定义的INOUT功能呢？困惑死了？在FPGA上也试过了 |
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