quartus 编写的硬件乘法器有错误求解。

只看该作者 · 2013-4-6 23:49

语句：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY 16jishu IS
GENERIC( WIDTHd: INTEGER:=16;
      WIDTHb:INTEGER:=16 );
port( clk,clrn,st : in std_logic;
   d    : IN std_logic_vector( WIDTHd-1 DOWNTO 0);
   b    : IN std_logic_vector ( WIDTHb-1 DOWNTO 0);
   A    : out std_logic_vector(WIDTHd+WIDTHb-1 DOWNTO 0);
   z    :  out std_logic
);
end 16jishu;
architecture one of 16jishu is
   TYPE ss IS(s0,s1,s2,s3 );
   signal state: ss:=s0;
   signal n : INTEGER RANGE WIDTHb DOWNTO 0;
   signal q : std_logic_vector(WIDTHd+WIDTHb downto 0);
   signal t : std_logic_vector(WIDTHb-1 downto 0);
begin
process (clk, clrn)
begin
if clrn = '0' then state<=s0;
   elsif (clk'event and clk = '1') then
   case state is
         when s0=>if st='1'then
            state<=s1;end if;
            when s1=>state<=s2;
            when s2=>if n=0 then state <=s3;
            else state <=s1;end if ;
            when s3=>state<=s0;
            when others =>state<=s0;
            end case;
            end if;
      end process;
   process (clk )
   VARIABLE cont :std_logic_vector(WIDTHd downto 0);
   begin
   if(clk'event and clk = '1') then
CASE state IS
   when s0 =>n<= WIDTHb;t<=b;z<='0';
   q<=(OTHERS =>'0');
   cont (WIDTHd downto 0):='0'&d(WIDTHd-1 DOWNTO 0);
   when s1=> n<=n-1;if t(0)='1' then
   q(WIDTHd+WIDTHb downto WIDTHb)<=q(WIDTHd + WIDTHb downto WIDTHb)
                                       +cont (WIDTHd downto 0);
                                       end if;
      when s2 =>t(WIDTHb-2 downto 0)<=t(WIDTHb-1 downto 1);
      t(WIDTHb-1)<='0';
   q(WIDTHd+WIDTHb -1 downto 0)<=q(WIDTHd+WIDTHb downto 1) ;
   q(WIDTHd+WIDTHb )<='0';
   when s3=> z<='1';
   q(WIDTHd+WIDTHb downto  1)<=q(WIDTHd+WIDTHb -1 downto 0);
   A<=q(WIDTHd+WIDTHb -1 downto 0);
   END CASE ;
   END IF;
   end process;
   END one;

Error (10500): VHDL syntax error at 16jishu.vhd(4) near text "16";  expecting an identifier