const RF_SETTINGS rfSettings =
{
0x00,
0x0B, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x10, // FREQ2 Frequency control word, high byte.
0xA7, // FREQ1 Frequency control word, middle byte.
0x62, // FREQ0 Frequency control word, low byte.
0x2D, // MDMCFG4 Modem configuration.
0x3B, // MDMCFG3 Modem configuration.
0x73, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x0A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x11, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x0B, // TEST0 Various test settings.
0x0B, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x05, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0x0c // PKTLEN Packet length.
};
void main()
{
WDTCTL = WDTPW + WDTHOLD;
InitSys();
P3DIR|=BIT0+BIT1+BIT3;
P4DIR|=BIT0;
P1SEL=0x00;
P3SEL=0x00;
CpuInit();
POWER_UP_RESET_CC2500();
halRfWriteRfSettings();
VER=halSpiReadReg(CCxxx0_SYNC1);
halSpiWriteBurstReg(CCxxx0_PATABLE,PaTabel,8);
while(1)
{
halSpiStrobe(CCxxx0_SIDLE);
halRfSendPacket(txBuffer,3);
delay(1000);
}
} |
楼主
标题置顶
标题高亮
