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采用Virtex5_FF1136_LX50T设计千兆网口,感觉FPGA没有工作啊

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cedarxiaomaoyu|  楼主 | 2013-5-11 13:39 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
求助求助~~~~
1.利用FPGA  Virtex5_FF1136_LX50T  进行千兆网口的设计,采用verilog语言,ISE13.2
2.代码采用的opencores网站上的tri_mode_ethernet代码
3.板子上已经焊接PHY芯片ET1011C2,PHY芯片与MAC层间以GMII的模式相连焊接,在ucf中将相应信号配置到实际的管脚上
   在开源代码中进行了如下修改:
             添加了PHY_reset信号,并且将该信号连接到板上的一个按键复位信号
             将Mdo,MdoEn合并成一个输入输出信号——inout Mdio:
                           assign  Mdio=MdoEn?Mdo:1'bz;
        现在,PHY芯片复位有反应,利用网线将千兆网口连接到PC的GE接口上可以连接上,但是本地连接显示:未识别的网络,请问这是为什么?
        PC的GE适配器已经设置为:流控制打开,速度和双工为自动侦测
        利用wireshark抓取数据包,cmd中利用arp -s连接IP地址和以太网MAC地址【这儿的以太网MAC地址怎么知道是多少,芯片固有还是怎么设置?】再利用cmd命令ping -w 1 -n 1 IP地址(自己设定的与本地连接IP相似的IP),wireshark只抓取到一个发送数据包,按理来说应该还有接收数据包,为什么没有收到呢?
        有人说是我的PHY芯片没有工作,但是我给ET1011C芯片设置了复位且复位有效,管理接口时钟Mdc在开源代码中由Host clock产生:见eth_clockgen.v代码,应该是没有错的啊?
         求各路大神指点啊?到底是哪儿出错了还是代码需要在哪儿修改什么的?

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GoldSunMonkey| | 2013-5-11 21:12 | 只看该作者
是不是代码有问题啊。
申请XILINX的一个评估版的license试一下。

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cedarxiaomaoyu|  楼主 | 2013-5-12 21:53 | 只看该作者
GoldSunMonkey 发表于 2013-5-11 21:12
是不是代码有问题啊。
申请XILINX的一个评估版的license试一下。

猴哥,这个是opencores上经过验证的代码,应该不会有错呢。由于没有权限发连接,不过这是代码描述:
Details
Name: ethernet_tri_mode
Created: Nov 25, 2005
Updated: Feb 18, 2013
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties
Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone Compliant: No
License: LGPL

Description
mail group is added to track all the Q&A from the author.
If you have any question about the design, please send your question to mail group. The answer will be recorded as reference for other people.
Group email: opencores-tri-mode-eth-mac@googlegroups.com


10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The whole project will be finished in TEN weeks inluding verilog coding,RTL level verification.
A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.


main Features
Ø Implements the full 802.3 specifiction.
Ø half-duplex support for 10 100 Mbps mode
Ø FIFO insterface to user application
Ø support pause frame generation and termination
Ø transmitting frames souce MAC address insertion
Ø receiving frames destination MAC address filter
Ø receiving broadcast frames throughout constraint
Ø support Jumbo frame 9.6K
Ø RMON MIB statistic counter


Project Status
- collect some documents about tri-mode ethernet MAC controller(done)
- coding in verilog(done)
- coding verification scripts(done)
- starting verification(done)
- writing specification(done)
- FPGA proven(done) 2006-06-20
- Supporting modelsim simulator. I also changed the default simulator from NC-sim to modelsim which is much populor than NC-sim :->. As well, the new version "dll" files for modelsim are ready. (done) 2008-7-26
- My next task is to connect this IP core to xilinx Microblaze processor.(done)2008-8-17
A new directory EDK was created in project root. All needed driver and EDF for EDK are available there.


Synthesis area report
##### START OF AREA REPORT #####
I/O ATOMs: 321

Total LUTs: 1839 of 10570 (17%)
Logic resources: 1839 ATOMs of 10570 (17%)
ATOM count by mode:
normal: 1555
arithmetic: 284

DSP Blocks: 0 (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 6 blocks (48 nine-bit).
ShiftTap: 0 (0 registers)
MRAM: 0 (0% of 1)
M4Ks: 0 (0% of 60)
M512s: 0 (0% of 94)
Total ESB: 0 bits
##### END OF AREA REPORT #####]


verification report
1. 1G mode ,46-1500 length packet sending and receiving was tested
2. 100M mode, 46-1500 length packet sending and receiving was tested
3. 10M mode , 46-1500 length packet sending and receiving was tested

place and route report
Logic Utilization:
Number of Slice Flip Flops: 1,198 out of 21,504 5%
Number of 4 input LUTs: 1,526 out of 21,504 7%
Logic Distribution:
Number of occupied Slices: 1,206 out of 10,752 11%
Number of Slices containing only related logic: 1,206 out of 1,206 100%
Number of Slices containing unrelated logic: 0 out of 1,206 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 1,555 out of 21,504 7%
Number used as logic: 1,526
Number used as a route-thru: 29
Number of bonded IOBs: 78 out of 448 17%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 2
Number used as BUFGCTRLs: 3
Number of FIFO16/RAMB16s: 4 out of 72 5%
Number used as FIFO16s: 0
Number used as RAMB16s: 4

Total equivalent gate count for design: 20,650
Additional JTAG gate count for IOBs: 3,744
Peak Memory Usage: 220 MB

求猴哥帮忙啊,主要是找不到问题在那边。。。猴哥要是有时间,可不可以加Q讨论下:1183211679

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GoldSunMonkey| | 2013-5-12 22:44 | 只看该作者
opencore上的不一定是验证过的。
我让你申请一个评估版的license,确定一下是什么问题。

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LMQQ| | 2013-5-12 22:58 | 只看该作者
俺猴哥说的对

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Tianya283| | 2013-5-12 23:01 | 只看该作者
;P

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GoldSunMonkey| | 2013-5-13 21:14 | 只看该作者
感谢大家的支持啊

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qin552011373| | 2013-5-13 21:30 | 只看该作者
GoldSunMonkey 发表于 2013-5-13 21:14
感谢大家的支持啊

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GoldSunMonkey| | 2013-5-14 13:55 | 只看该作者
qin552011373 发表于 2013-5-13 21:30

和尚啊

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cedarxiaomaoyu|  楼主 | 2013-5-14 23:59 | 只看该作者
GoldSunMonkey 发表于 2013-5-13 21:14
感谢大家的支持啊

多谢猴哥,现在wireshark已经能够抓到FPGA发送的数据了~~~
但是要具体实现该千兆网口的应用,还要初始化PHY芯片。可是ET1011C芯片手头只有datasheet,不大清楚该芯片初始化需要写哪些东西,猴哥可以指出一些初始化编写方向吗?

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GoldSunMonkey| | 2013-5-15 15:04 | 只看该作者
cedarxiaomaoyu 发表于 2013-5-14 23:59
多谢猴哥,现在wireshark已经能够抓到FPGA发送的数据了~~~
但是要具体实现该千兆网口的应用,还要初始化P ...

我每次直连即可。没有初始化过啊

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cedarxiaomaoyu|  楼主 | 2013-5-15 22:13 | 只看该作者
GoldSunMonkey 发表于 2013-5-15 15:04
我每次直连即可。没有初始化过啊

MAC层不是需要通过Mdc和Mdio两个接口读取ET1011C芯片寄存器中的数据吗?就是像别人写的发送/接收状态机eth_statem之类的。就是这几个地方有点不清楚。如果不需要初始化,那么是不是只要通过IP核实例化直接生成GMII等相关接口,然后通过GMII接口信号连接MAC层到PHY芯片,并通过Mdc和Mdio管理PHY芯片的数据?【这个管理数据时什么意思啊?是直接将FPGA程序中的Mdc(如2.5MHz)绑定到FPGA相关管脚就行了吗?】

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旅途尽美| | 2013-12-24 09:56 | 只看该作者
现在用virtex6,实现FPGA与PC的通信,遇到同样的困惑啊,chipscope抓包分析TEMAC发往PHY芯片88E1111的数据都是没有错的,封装的UDP数据格式也是对的,但PC端的wireshark就是抓不到数据啊?怎么办呢?

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