entity TWO is
port
(
clk1_ref :in std_logic;
clk2_ref :in std_logic;
flag :out std_logic;
);
end TWO;
architecture TWO_body of TWO is
begin
process(clk1_ref)
begin
if(clk1_ref'event and clk1_ref='0')then
flag <='0';
if clk2_ref='1' then
flag <='1';
end if;
end if;
end process;
end TWO_body;
VHDL语言,一个进程中只能有一个沿触发,因此第二个信号是电平检测,初学者的一点儿意见,欢迎指正