（VHDL）奇数或偶数分频器如何设计？还有占空比怎么设计的啊？

只看该作者 · 2013-7-9 21:08

这个程序对么是奇分频还是偶分频啊？
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fpq is
port(
   clk:in std_logic;
   clkout:out std_logic);
end entity fpq;
architecture one of fqp is
signal cnt:std_logic_vector(1 downto 0);
begin
process（clk）
veriable cnt:integer range 0 to 3;
begin
if rising_edge(clk) then
  if cnt=3
then cnt :=0;
else cnt :=cnt+1;
end if;
if cnt< 2
  then clkout< ='0';
else clkout<='1';
end if;
end if;
end process;
end architecture one;
下面这个是占空比50%的  请问占空比怎么更改啊？
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fpq is
port(
   clk:in std_logic;
   clkout:out std_logic);
end entity fpq;
architecture one of fqp is
signal cnt:std_logic_vector(1 downto 0);
begin
process（clk）
begin
if rising_edge(clk) then
  if cnt="11"
then clkout<="00";
else cnt <=cnt+1;
end if;
if cnt="00"or cnt="01"
  then clkout< ='0';
else clkout<='1';
eng if;
end if;
end process;
end architecture one;
谢谢大家帮个忙哦嘿嘿