下面的VHDL代码,testbench该怎么写? 可以贴一下吗?
-- D触发器
libarary ieee ; use ieee std_logic_1164.all ; entity tdff is port ( clk, d : in std_logic ; q : out std_logic ) ; end tdff ; architecture behaviour of tdff is begin process(clk) begin if ( clk'event and clk = '1' ) then q <= d ; end process ; end behaviour ;
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