library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a1,b1 : in std_logic;
c1 : out std_logic
);
end or2;
architecture one of or2 is
begin
c1<=(a1 or b1);
end one;
library ieee;
use ieee.std_logic_1164.all;
entity h_adder is
port(
a,b : in std_logic;
co,so : out std_logic
);
end h_adder;
architecture one of h_adder is
begin
so<=(a or b) and (a nand b);
co<=not (a nand b);
end one;
library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
port(
ain,bin,cin : in std_logic;
cout,sum : out std_logic
);
end f_adder;
architecture one of f_adder is
component or2
port(
a1,b1 : in std_logic;
c1 : out std_logic
);
end component;
component h_adder
port(
a,b : in std_logic;
co,so : out std_logic
);
end component;
signal d,e,f : std_logic;
begin
u1 : h_adder port map(a=>ain,b=>bin,co=>d,so=>e);
u2 : h_adder port map(a=>e,b=>cin,co=>f,so=>sum);
u3 : or2 port map(a1=>d,b1=>f,c1=>cout);
end one;
分别保存后，在综合的时候出现
symbolic name "a1"is not a port of "or2"in a vhdl design file
symbolic name "b1"is not a port of "or2"in a vhdl design file
symbolic name "c1"is not a port of "or2"in a vhdl design file
暑假自学中有点迷茫哈，谢谢大虾指导。 |
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