大家来聊聊这三款CPU.它们性能如何,能否做个比较.下面是性能比较列表。
这三种中，OR1K,LEON,都是开源的，MIPS用的较多，是否开源？我没找到。
MIPS32 4KE :
32-bit MIPS32 privileged resource architecture
32-bit address and data paths
5-stage pipeline
32 general purpose registers
Supervisor mode operation
MIPS32-compatible instruction set
MIPS16e code compression
Special PC-relative instructions for efficient loading of addresses and constants
SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines
Programmable cache sizes
Individually configurable instruction and data caches, sizes from 0 - 64KB
Direct mapped, 2-, 3-, or 4-way set associative
Loads block only until critical word is available
Non-blocking prefetches
Write-back support
16-byte cache line size
Memory management unit
16 dual entry JTLB with variable page size
Fixed or TLB-based MMU, dependent on family member
Scratchpad RAM support
Can optionally replace 1 way of the I- and/or D-cache with a fast scratchpad RAM
20 index address bits allow access of arrays up to 1MB
Interface allows back-stalling the core
Simple bus interface unit (BIU)
All I/Os fully registered
Separate unidirectional 32-bit address and data buses
Two 16-byte collapsing write buffers
Designed to allow easy conversion to other bus protocols
Integer multiply/divide unit e
Fast or area efficient MDU, dependent on family member
Maximum issue rate of one 32x16 multiply per clock (fast MDU)
Maximum issue rate of one 32x32 multiply every other clock (fast MDU)
General purpose coprocessor (COP2) interface
32-bit interface to an external coprocessor
Power control
Minimum frequency: 0 MHz
Power-down mode (triggered by WAIT instruction)
Support for software-controlled clock divider
Support for extensive use of local gated clocks
EJTAG debug
Support for single stepping
Virtual instruction and data address breakpoints
PC and data tracing
Benefits :
Process: 0.13um G
Frequency Typical: 260-300MHz
Frequency Worst-case: 210-255MHz
Typical Performance 405 Dhrystone MIPS
Power Consumption: 0.12 - 0.37 mW/MHz at 1.2V (Core Only)
Core Size: 0.4 - 1.9 mm(2) (core only)
Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries.
:LEON3:
The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The LEON3 processor has the following features:
SPARC V8 instruction set with V8e extensions
Advanced 7-stage pipeline
Hardware multiply, divide and MAC units
High-performance, fully pipelined IEEE-754 FPU
Separate instruction and data cache (Harvard architecture) with snooping
Configurable caches: 1 - 4 sets, 1 - 256 kbytes/set. Random, LRR or LRU replacement
Local instruction and data scratch pad rams
SPARC Reference MMU (SRMMU) with configurable TLB
AMBA-2.0 AHB bus interface
Advanced on-chip debug support with instruction and data trace buffer
Symmetric Multi-processor support (SMP)
Power-down mode
Robust and fully synchronous single-edge clock design
Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
Fault-tolerant and SEU-proof version available for space applications
Extensively configurable
Large range of software tools: compilers, kernels, simulators and debug monitors
The LEON3 processor is distributed as part of the GRLIB IP library, allowing simple integration into complex SOC designs. GRLIB also includes a configurable LEON3 multi-processor design, with up to 4 CPU's and a large range of on-chip peripheral blocks.
OpenRISC 1000 :
The OpenRISC 1000 architecture is the latest in
the development of modern open architectures
and the base for a family of 32- and 64-bit
RISC/DSP processors. Open architecture allows
a spectrum of chip and system implementations
at a variety of price/performance points for a
range of applications. Designed with emphasis
on performance, simplicity, low power
consumption, scalability, and versatility, it
targets medium and high performance
networking, portable, embedded, and automotive
applications.
High Performance 32-Bit CPU/DSP
· 32-bit architecture implementing ORBIS32
instruction set
· Scalar, single-issue 5-stage pipeline
delivering sustained throughput
· Single-cycle instruction execution on most
instructions
· 250 MIPS performance @ 250MHz worstcase
conditions
· Predictable execution rate for hard real-time
applications
· Fast and deterministic internal interrupt
response
· Thirty-two, 32-bit general-purpose registers
· DSP MAC 32x32
· Custom user instructions
L1 Caches
· Harvard model with split instruction and
data cache
· Instruction/data cache size scalable from
1KB to 64KB
· Physically tagged and addressed
· Cache management special-purpose
registers
Memory Management Unit
· Harvard model with split instruction and
data MMU
· Instruction/data TLB size scalable from 16
to 256 entries
· Direct-mapped hash-based TLB
· Linear address space with 32-bit virtual
address and physical address from 24 to 32
bits
· Page size 8KB with per-page attributes
Sophisticated Power Management Unit
· Power reduction from 2x to 100x
· Software controlled clock frequency in slow
and idle modes
· Interrupt wake-up in doze and sleep modes
· Dynamic clock gating for individual units
Advanced Debug Unit
· Conventional target-debug agent with a
debug exception handler
· Non-intrusive debug/trace for both RISC
and system
· Real-time trace of RISC and system
· Access and control of debug unit from RISC
or via development interface
· Complex chained watchpoint and breakpoint
conditions
Integrated Tick Timer
· Task scheduling and precise time measuring
· Maximum timer range of 2^32 clock cycles
· Maskable tick-timer interrupt
· Single-run, restartable or continuous mode
Programmable Interrupt Controller
· 2 non-maskable interrupt sources
· 30 maskable interrupt sources
· two interrupt priorities
Custom and Optional Units
· Additional units such as a floating-point unit
can be added as standard units
· 8 custom units can be added and controlled
through special-purpose registers or
customer instructions
Specifications
· 250 MHz in worst-case 0.18u 6LM
The OpenRISC 1200 Processor Core is ideally
suited for applications that require 32-bit
performance compared to performance of 16-bit
processors and need low cost and low power
consumption advantage compared to 64-bit
processors.
· 250 MIPS Dhrystone 2.1 @ 250MHz wc
· 250 MMAC operations @ 250MHz wc
· <1W @ 250MHz, 0.18u, full throttle (est)
· <500mW @ 250MHz, 0.18u, half throttle
(est)
· Area <0.5 sqmm @ 0.18u 6LM (cache
memories not included)
Target Applications
· Internet, networking and telecom
applications
· Embedded applications
· Portable and wireless applications
· Home entertainment consumer electronics
· Automotive applications |
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