求大虾们指点迷津，看看哪错了

只看该作者 · 2013-8-20 17:03

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity  AS is
PORT ( CLK  :  IN  STD_LOGIC;
   key  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
   duan  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
   wei : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end ;
ARCHITECTURE bhv OF AS IS
signal tmp: std_logic_vector(3 downto 0);
begin
process(CLK)
variable  n:integer range  0 to 19;
begin
if  rising_edge(CLK) then  n:=n+1;
  if n<=4  then tmp<="1110";
elsif n<=9 and  n>4  then
   tmp<="1101";
   elsif n<=14 and n>9  then
      tmp<="1011";
      else
         tmp<="0111";
         n:=0;
      end if;
   end  if;
   end  if;
end process;
PROCESS( tmp )
begin
  wei<="11111111" ;
tmp<=key;
CASE  tmp IS
WHEN "1110" =>wei<="11111110";duan <= "11111001"; --  1--按下key1数码管显示1
WHEN "1101" =>wei<="11111101";duan <= "10100100"; --  2--按下key2数码管显示2
WHEN "1011" =>wei<="11111011";duan <= "10110000"; --  3--按下key3数码管显示3
WHEN "0111" =>wei<="11110111";duan <= "10011001"; --  4--按下key4数码管显示4
WHEN OTHERS =>  duan <= "11111111";
END CASE ;
  END PROCESS ;
END ;