Warning: Verilog HDL Always Construct warning at maincontrol.v(91): variable "NEXT_state" may not be assigned a new value in every possible path through the Always Construct. Variable "NEXT_state" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
请问各位大侠怎么会造成这个问题的？应该怎么解决～～小弟多谢了～～
我用的是Verilog HDL |
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