2812的为啥倍频不起作用

只看该作者 · 2013-8-25 23:06

2812采用30MHz晶振，5倍频，时钟应是150M，但实际上倍频没有作用，时钟还是30M，请问可能的原因在哪儿。还有就是DSP2812的140脚XF_PLL的引脚应该怎么接

只看该作者 · 2013-8-25 23:14

倍频要在程序里倍啊。。

// This function initializes the PLLCR register.

void Init_Pll(UINT val)

{

volatile Uint16 iVol;

PllVal = (val/2);

if (*SYSCTRL_REG_PLLCR != val)

{

   EALLOW;

   *SYSCTRL_REG_PLLCR = val;

   EDIS;

// Optional: Wait for PLL to lock.

// During this time the CPU will switch to OSCCLK/2 until the PLL is

// stable.  Once the PLL is stable the CPU will switch to the new PLL value.

//

// This switch time is 131072 CLKIN cycles as of Rev C silicon.

//

// Code is not required to sit and wait for the PLL to lock.

// However, if the code does anything that is timing critical,

// and requires the correct clock be locked, then it is best to

// wait until this switching has completed.

// If this function is run from waitstated memory, then the loop count can

// be reduced as long as the minimum switch time is still met.

// iVol is volatile so the compiler will not optimize this loop out

//

// The watchdog should be disabled before this loop, or fed within

// the loop.

   DisableDog();

// Wait lock cycles.

// Note,  This loop is tuned to 0-waitstate RAM memory.  If this

// function is run from wait-stated memory such as Flash or XINTF,

// then the number of times through the loop can be reduced

// accordingly.

   for(iVol= 0; iVol< ( (131072/2)/12 ); iVol++)

   {

   }

}

}