用 estimate_test_coverage 结果 Loading target library 'slow' Loading design ... Using test protocol in memory. Starting test coverage estimation ... Error: Can not get fault coverage for design PPM_TOP due to design rule checking error. 然后check_dft ************************************************** Test Design Rule Violation Summary
Total violations: 69 **************************************************
PROTOCOL VIOLATIONS 35 Asynchronous pins uncontrollable violations (TEST-116) 15 Asynchronous signal active during scan violations (TEST-280) SCAN IN VIOLATIONS 15 Cell constant during scan violations (TEST-142) 1 Cell is uncontrollable during scan violation (TEST-302) CAPTURE VIOLATIONS 2 Unreliable capture (async pin) violations (TEST-471) 1 Cell does not capture violation (TEST-310)
************************************************** Sequential Cell Summary
43 out of 1179 sequential cells have violations **************************************************
简单描述下设计,异步复位,一个全局时钟,内部有复位逻辑,是同步的。 我列举几个DRC违例,想请问下如何解决,DFT我是第一次作。每类问题我列一个出来问,请教下如何解决,详细的DRC警告见附件: 1.Warning: Cell uart_top1/tx232/m1_state_reg_1_0 (SDFFNRX1) is always asynchronously set/cleared. (TEST-280) 2.Warning: Asynchronous pins of cell uart_top1/tx232/data_in_waiting_reg_0_0 (SDFFNSRX2) are uncontrollable. (TEST-116) 3.Warning: Sequential cell uart_top1/tx232/q_reg_1_0 (SDFFNSX1) has constant logic 1/0 state. (TEST-142) 4.Warning: Cell gen_sclk1/Phase_cnt_reg_0_0 (SDFFNSRX4) is not scan controllable. (TEST-302) 5.Warning:Asynchronous control pin SN of cellgen_sclk1/Phase_cnt_reg_0_0(SDFFNSRX4) can change in the capture cycle.This can cause the cell tocapture unreliably. (TEST-471) 6.Warning: Data can not be captured into cell gen_sclk1/Phase_cnt_reg_0_0 (SDFFNSRX4). (TEST-310) ...binding scan-out state... |