以下是我的源文件：
`timescale 1ns / 10psmodule Keyscan (sclk,rst_n,sw1_n,sw2_n,
sw3_n,sw4_n,sw5_n,led_n);
input sclk; //系统时钟 50MHz
input rst_n; //全局复位管脚
input sw1_n,sw2_n, //五个按键——低电平有效
sw3_n,sw4_n,sw5_n;
output[4:0] led_n; //5个LED——低电平亮
//--------------------------------------------------------------
reg[4:0] sw_rst;
always @ ( posedge sclk or negedge rst_n )
begin
if(!rst_n)
sw_rst <= 5'b11111;
else
sw_rst <= {sw5_n,sw4_n,sw3_n,sw2_n,sw1_n};
end
//---------------------------------------------------------------
reg[4:0] sw_rst_r;
always @ ( posedge sclk or negedge rst_n )
begin
if(!rst_n)
sw_rst_r <= 5'b11111;
else sw_rst_r <= sw_rst;
end
//----------------------------------------------------------------
wire[4:0] key_en = sw_rst_r & (~sw_rst);
reg[19:0] cnt;
always @ ( posedge sclk or negedge rst_n )
begin
if(!rst_n)
cnt <= 20'd0;
else if(key_en)
cnt <= 20'd0;
else cnt <= cnt +1'b1;
end
//-----------------------------------------------------------
reg[4:0] low_sw;
always @ ( posedge sclk or negedge rst_n )
begin
if(!rst_n)
low_sw <= 5'b11111;
else if(cnt == 20'hfffff)
low_sw <= {sw5_n,sw4_n,
sw3_n,sw2_n,sw1_n};
end
reg[4:0] low_sw_r;
always @ ( posedge sclk or negedge rst_n )
begin
if(!rst_n)
low_sw_r <= 5'b11111;
else low_sw_r <= low_sw;
end
wire[4:0] led_ctrl = low_sw & (~low_sw_r);
reg[4:0] led;
always @ ( posedge sclk or negedge rst_n )
begin
if(!rst_n)
led <= 5'b11111;
else if(led_ctrl[0])
led[0] <= ~led[0];
else if(led_ctrl[1])
led[1] <= ~led[1];
else if(led_ctrl[2])
led[2] <= ~led[2];
else if(led_ctrl[3])
led[3] <= ~led[3];
else if(led_ctrl[4])
led[4] <= ~led[4];
end
assign led_n[0] = led[0] ? 1'b1:1'b0;
assign led_n[1] = led[1] ? 1'b1:1'b0;
assign led_n[2] = led[2] ? 1'b1:1'b0;
assign led_n[3] = led[3] ? 1'b1:1'b0;
assign led_n[4] = led[4] ? 1'b1:1'b0;
endmodule
以下是Testbench脚本：
timescale 1ns/1ns //时间单位/精度
module Keyscan_tb;
reg sclk;
reg rst_n;
reg sw1_n,sw2_n, //五个按键——低电平有效
sw3_n,sw4_n,sw5_n;
wire[4:0] led_n;
/*-----------------------------------------------------
建立module 名 设置输入为reg 输出为 wire
------------------------------------------------------*/
Keyscan I_Keyscan
(
.sclk (sclk ),
.rst_n (rst_n),
.sw1_n (sw1_n),
.sw2_n (sw1_n),
.sw3_n (sw1_n),
.sw4_n (sw1_n),
.sw5_n (sw5_n),
.led_n (led_n)
);
// 例化 module
always #10 sclk = ~ sclk;
//设置 时钟
/*----------------------------------------------------------
* 初始化相应的变量，并设定激励输入
----------------------------------------------------------*/
initial
begin
$monitor("%d,\t%b,%b,%b,%b,%b,\t%d",$time, sclk,sw5_n,sw4_n,sw3_n,sw2_n,sw1_n,led_n);
#0 sclk = 0;
rst_n = 0;
sw1_n = 1;
sw2_n = 1;
sw3_n = 1;
sw4_n = 1;
sw5_n = 1;
#100 rst_n = 1;
end
initial
begin
#200 sw1_n = 0;
#300 sw2_n = 0;
#400 sw3_n = 0;
#500 sw4_n = 0;
#600 sw5_n = 0;
#350000 sw1_n = 1;
#360000 sw2_n = 1;
#370000 sw3_n = 1;
#380000 sw4_n = 1;
#390000 sw5_n = 1;
end
endmodule
以下是do文件：
vlib work
#新建一个库
vmap work work
#目前的逻辑工作库work和实际工作库work映射对应
vlog ../modelsim/src/Keyscan.v
#编译Keyscan.v(/……/为其相对路径）
vlog ../modelsim/Testbench/Keyscan_tb.v
#编译Keyscan_tb.v
vsim -novopt work.Keyscan_tb
#仿真测试脚本不优化
add wave-hex/I_Keyscan/ *
#调出波形，并以十六精制显示，显示I_Keyscan下的端口
run 3ms
#运行3ms 停下
但运行do文件之后调出的只是外部波形，图如下：谁能帮我解决下怎样调出内部波形。
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