就是一段VHDL程序设计遥控编码器电路,发送编码“101100”,不论键按下的持续时间多长(大于一个时钟周期),都只发送一次编码,按键按下到发送编码之间时间不限
这是我写的源码:这个编译是通过的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity d1 is
port(
clk: in std_logic;
key: in std_logic;
dout: out std_logic
);
end entity d1;
architecture d1_1 of d1 is
signal state:std_logic_vector(2 downto 0);
begin
statep: process(clk) is
begin
if clk'event and clk='1' then
case state is
when "000"=>
if key='0' then
state<="000";
else
state<="001";
end if;
when "001"=>
state<="010";
when "010"=>
state<="011";
when "011"=>
state<="100";
when "100"=>
state<="101";
when "101"=>
state<="110";
when "110"=>
if key='1' then
state<="110";
else
state<="000";
end if;
when others=>state<="000";
end case;
end if;
end process;
gp: process(state) is
begin
case state is
when "000"=>dout<='0';
when "001"=>dout<='1';
when "010"=>dout<='0';
when "011"=>dout<='1';
when "100"=>dout<='1';
when "101"=>dout<='0';
when "110"=>dout<='0';
when others=>dout<='0';
end case;
end process;
end architecture d1_1;
然后这个是测试码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity d1_test is
end entity d1_test;
architecture d1_test_1 of d1_test is
component d1 is
port(
clk: in std_logic;
key: in std_logic;
dout: out std_logic
);
end component d1;
signal clk1: std_logic:='0';
signal key1: std_logic:='0';
signal dout1: std_logic;
begin
d1_module: d1 port map(clk=>clk1,key=>key1,dout=>dout1);
simprocess:process
begin
key1<='0';
wait for 100ns;
key1<='1';
wait for 1600ns;
key1<='0';
end process;
clkprocess:process
begin
clk1<=not clk1 after 50ns;
end process;
end architecture d1_test_1;
编译时没错有3个warning
然后仿真时怎么都没有波形,wave上面的变量永远是nodata,而且过一下就死机,已经弄了一下午了,求助大牛们花一点点时间看看是哪里错了,感激不尽啊
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