RTC: 32.768-kHZ Clock is Gating Off
Revisions Affected 1.0
Details The RTC has a clock gating issue that stops the internal 32.768-kHz clock when the
VDD_CORE voltage domain drops below the recommended operating range or the
PWRONRSTn input terminal is held low. This issue has the following side effects:
• The RTC counters stop incrementing when the 32.768-kHz clock is gated. This
causes the RTC to lose time while the clock is gated.
• A wakeup event applied to the EXT_WAKEUP input terminal is masked if the
EXT_WAKEUP_DB_EN bit in the RTC PMIC register (0x98) is set to 1 which enables
the de-bounce function for the EXT_WAKEUP input. This occurs because the
32.768-kHz clock is being used to clock the de-bounce circuit.
Workarounds Do not turn off the VDD_CORE power source or source a logic low to the PWRONRSTn input while expecting RTC to keep an accurate time.
Do not enable the de-bounce circuit on the EXT_WAKEUP input if an external wakeup
event needs to be detected while the 32.768-kHz clock is gated.
内部的RTC竟然无法使用。 |