module IR_OF_MINE(clk,rstn,ir_in,data_out);
input clk;
input rstn;
input ir_in;
output [0:31]data_out;
/****1ms，2ms，3ms分别为接收端0.565ms,1.685,2.25,4.5之间的分界********/
parameter boundary1=18'd5_000; //1ms
parameter boundary2=18'd10_000; //2ms
parameter boundary3=18'd15_000; //3ms
parameter boundary4=18'd25_000; //4ms
/***********/
reg [0:31]data;
reg [17:0]cnt;
reg [5:0]i;
reg en;
wire en_record;
wire bit_record;
reg bit_read;
/******以下用来产生ir的上升（clr）和下降(record)信号*******/
wire clr;
wire record;
reg ir_f1;
reg ir_f2;
reg ir_f3;
reg ir_f4;
always@(posedge clk or negedge rstn)
begin
if(!rstn)
begin
ir_f1<=1'b0;
ir_f2<=1'b0;
ir_f3<=1'b0;
ir_f4<=1'b0;
end
else
begin
ir_f1<=ir_in;
ir_f2<=ir_f1;
ir_f3<=ir_f2;
ir_f4<=ir_f3;
end
end
assign clr=!ir_f2&ir_f1;
assign en_record=!ir_f1&ir_f2;
assign bit_record=!ir_f2&ir_f3;
assign record=!ir_f3&ir_f4;
/*****以下是cnt的计数功能******/
always @(posedge clk or negedge rstn)
begin
if(!rstn)
cnt<=18'd0;
else if(cnt==18'd250_000)
cnt<=18'd0;
else if(clr)
cnt<=18'd0;
else if(ir_in)
cnt<=cnt+1'b1;
end
always@(posedge clk or negedge rstn)
begin
if(!rstn)
en<=0;
else if(en_record & cnt>boundary3)
begin
en<=1;
data<=32'd0;
end
else if(en_record & cnt>boundary2 & cnt<boundary3)
en<=0;
end
always@(posedge clk or negedge rstn)
begin
if(!rstn)
i<=6'd0;
else if(en & bit_record)
begin
if(cnt<boundary1)
bit_read<=0;
else if(cnt>boundary1 & cnt<boundary2)
bit_read<=1;
end
end
always@(posedge clk or negedge rstn)
begin
if(!rstn)
i<=0;
else
begin
case(i)
6'd0,6'd1,6'd2,6'd3:
if(record)
begin
data[i]<=bit_read;
i<=i+1;
end
endcase
end
end
assign data_out=data;
endmodule |
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