fpga的计数问题

只看该作者 · 2014-3-20 16:51

前几天发了个电机的程序  还是没能解决啊~~~照着版主的办法还是没能解决测速的显示问题  然后摘出计数部分果然是这个问题换了数码管初值也不行  一直都是全输出  为8
module jishu(HEX1,HEX2,HEX3,HEX4,clk1,rst);
output [6:0] HEX1,HEX2,HEX3,HEX4;
input rst,clk1;
reg [31:0]en;

/*************************************/
reg [3:0] cs_ge;
reg [3:0] cs_shi;
reg [3:0] cs_bai;
reg [3:0] cs_qian;

always@(posedge clk1 or negedge rst)
if  (!rst) en<=0;
else
if (en==27000000)
      en<=0;
else
   en<=en+1;

always@(posedge clk1 or negedge rst)
if  (!rst) cs_ge<=0;
else
begin
if(cs_ge>9)
   cs_ge<=0;
else if (en==0)
   cs_ge<=cs_ge+1;
else
   cs_ge<=cs_ge;
end
always@(posedge clk1 or negedge rst)
if  (!rst) cs_shi<=0;
else
begin
if(cs_shi>9)
   cs_shi<=0;
else if((cs_ge==9)&(en==0))
   cs_shi<=cs_shi+1;
else
   cs_shi<=cs_shi;
end

always@(posedge clk1 or negedge rst)
if  (!rst) cs_bai<=0;
else
begin
if(cs_bai>9)
   cs_bai<=0;
else if ((cs_ge==9)&(cs_shi==9)&(en==0))
   cs_bai<=cs_bai+1;
else
   cs_bai<=cs_bai;
   end
always@(posedge clk1 or negedge rst)
if  (!rst) cs_qian<=0;
else
begin
if (cs_qian==9)cs_qian<=0;
else if((cs_ge==9)&(cs_shi==9)&(cs_bai==9)&(en==0))
      cs_qian<=cs_qian+1;
else
      cs_qian<=cs_qian;
end


/***************************************/
smg m1(.hex11(hex001),.clkk(clk1),.smg_zhi(cs_qian),.rstt(rst));
smg m2(.hex11(hex002),.clkk(clk1),.smg_zhi(cs_bai),.rstt(rst));
smg m3(.hex11(hex003),.clkk(clk1),.smg_zhi(cs_shi),.rstt(rst));
smg m4(.hex11(hex004),.clkk(clk1),.smg_zhi(cs_ge),.rstt(rst));
/***************************************/
endmodule

module smg(hex11,clkk,smg_zhi,rstt);
input rstt;
output hex11;
wire [6:0]hex11;
reg [6:0]hex;
input clkk;
assign hex11=hex;
parameter seg0=~7'h3f,
   seg1=~7'h06,
   seg2=~7'h5b,
   seg3=~7'h4f,
   seg4=~7'h66,
   seg5=~7'h6d,
   seg6=~7'h7d,
   seg7=~7'h07,
   seg8=~7'h7f,
   seg9=~7'h6f,
   sega=~7'h77,
   segb=~7'h7c,
   segc=~7'h39,
   segd=~7'h5e,
   sege=~7'h79,
   segf=~7'h71;
input [3:0] smg_zhi;
always @ (posedge clkk or negedge rstt )
if(!rstt) hex<=seg0;
else

  case (smg_zhi)
4'd0:hex=seg0;
4'd1:hex=seg1;
4'd2:hex=seg2;
4'd3:hex=seg3;
4'd4:hex=seg4;
4'd5:hex=seg5;
4'd6:hex=seg6;
4'd7:hex=seg7;
4'd8:hex=seg8;
4'd9:hex=seg9;
endcase

endmodule