TIM1 DMA Transfer example -------------------------------------------------
TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
and Connectivity line devices and to 24 MHz for Low-Density Value line and
Medium-Density Value line devices.
The objective is to configure TIM1 channel 3 to generate complementary PWM
signal with a frequency equal to 17.57 KHz:
- TIM1_Period = (SystemCoreClock / 17570) - 1
and a variable duty cycle that is changed by the DMA after a specific number of
Update DMA request.
The number of this repetitive requests is defined by the TIM1 Repetition counter,
each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new
value defined by the SRC_Buffer .
/* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
TimerPeriod = (SystemCoreClock / 17570 ) - 1;
/* Compute CCR1 value to generate a duty cycle at 50% */
SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
/* Compute CCR1 value to generate a duty cycle at 37.5% */
SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
/* Compute CCR1 value to generate a duty cycle at 25% */
SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
大概意思就是每产生三个更新请求就把SRC_Buffer的值通过DMA传送到比较寄存器。但是实际运行时占空比一直是37.5，通过串口打印出的结果也一直没变。这是什么原因？按理说占空比应该不断变化，从50、37.5、25
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