TI CCS5.4上给的例程，默认情况下，如果没有对msp430f5529的时钟进行配置的话，MCLK=SMCLK=1MHz，ACLK=32.768KHz，例程使用的spi时选取SMCLK为时钟源，并对其进行二分频，有关代码如下 ：
UCA0CTL1 |= UCSSEL_2; // SMCLKUCA0BR0 = 0x02; // /2
UCA0BR1 = 0; //
例程的spi时钟输出端为P2.7
如果按照user's guide的描述，spi主模式下，P2.7输出的时钟频率应该在500KHz左右
但是使用示波器测P2.7引脚的频率只有35kHz左右
提高DCO的频率的时候，该引脚的频率也已相同倍数的增加，我把片内DCO调到8MHz，P2.7引脚的时钟输出也变成了原来的8倍，到了277KHz左右，但是不是SMCLK的一半（4MHz)
我始终想不明白，望大神帮忙解答
以下是完整的例程代码：
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//******************************************************************************
// MSP430F552x Demo - USCI_A0, SPI 3-Wire Master Incremented Data
//
// Description: SPI master talks to SPI slave using 3-wire mode. Incrementing
// data is sent by the master starting at 0x01. Received data is expected to
// be same as the previous transmission. USCI RX ISR is used to handle
// communication with the CPU, normally in LPM0. If high, P1.0 indicates
// valid data reception. Because all execution after LPM0 is in ISRs,
// initialization waits for DCO to stabilize against ACLK.
// ACLK = ~32.768kHz, MCLK = SMCLK = DCO ~ 1048kHz. BRCLK = SMCLK/2
//
// Use with SPI Slave Data Echo code example. If slave is in debug mode, P1.1
// slave reset signal conflicts with slave's JTAG; to work around, use IAR's
// "Release JTAG on Go" on slave device. If breakpoints are set in
// slave RX ISR, master must stopped also to avoid overrunning slave
// RXBUF.
//
// MSP430F552x
// -----------------
// /|\| |
// | | |
// --|RST P1.0|-> LED
// | |
// | P3.4|-> Data Out (UCA0SIMO)
// | |
// | P3.5|<- Data In (UCA0SOMI)
// | |
// Slave reset <-|P1.1 P3.0|-> Serial Clock Out (UCA0CLK)
//
//
// Bhargavi Nisarga
// Texas Instruments Inc.
// April 2009
// Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430.h>
unsigned char MST_Data,SLV_Data;
unsigned char temp;
int main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
P1OUT |= 0x02; // Set P1.0 for LED
// Set P1.1 for slave reset
P1DIR |= 0x03; // Set P1.0-2 to output direction
P3SEL |= BIT3+BIT4; // P3.3,4 option select
P2SEL |= BIT7; // P2.7 option select
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 0x02; // /2
UCA0BR1 = 0; //
UCA0MCTL = 0; // No modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
P1OUT &= ~0x02; // Now with SPI signals initialized,
P1OUT |= 0x02; // reset slave
for(i=50;i>0;i--); // Wait for slave to initialize
MST_Data = 0x01; // Initialize data values
SLV_Data = 0x00; //
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = MST_Data; // Transmit first character
__bis_SR_register(LPM0_bits + GIE); // CPU off, enable interrupts
}
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
volatile unsigned int i;
switch(__even_in_range(UCA0IV,4))
{
case 0: break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
if (UCA0RXBUF==SLV_Data) // Test for correct character RX'd
P1OUT |= 0x01; // If correct, light LED
else
P1OUT &= ~0x01; // If incorrect, clear LED
MST_Data++; // Increment data
SLV_Data++;
UCA0TXBUF = MST_Data; // Send next value
for(i = 20; i>0; i--); // Add time between transmissions to
// make sure slave can process information
break;
case 4: break; // Vector 4 - TXIFG
default: break;
}
}
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