程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity my_dff is
Port (
clk_a : in STD_LOGIC;
reset_a : in STD_LOGIC;
sync_in : in STD_LOGIC;
comp_data_a : out std_logic_vector(31 downto 0);
comp_data_b : out std_logic_vector(31 downto 0)
);
end my_dff;
architecture Behavioral of my_dff is
signal s_sync_in : std_logic;
signal s_comp_count : std_logic_vector(2 downto 0);
--signal s_comp_count : std_logic_vector(1 downto 0);
signal s_comp_data_a : std_logic_vector(31 downto 0);
signal s_comp_data_b : std_logic_vector(31 downto 0);
begin
comp_data_a <= s_comp_data_a;
comp_data_b <= s_comp_data_b;
dpram_dual_clock_b_p: process(clk_a,reset_a)
begin
if(reset_a ='1')then
s_sync_in <= '0';
s_comp_count <= "100";
--s_comp_count <= "11";
s_comp_data_a <=(others => '0');
s_comp_data_b <=(others => '0');
elsif (clk_a'event and clk_a = '1') then
--if(s_comp_count /="11")then
if(s_comp_count /="100")then
s_comp_count <= s_comp_count + 1;
else
s_sync_in <= '0';
end if;
if (sync_in = '1') then
s_comp_count <= "000";
--s_comp_count <= "000";
s_sync_in <= '1';
end if;
if(s_sync_in ='1')then
case s_comp_count is
when "000" =>
--when "00" =>
s_comp_data_a(7 downto 0) <= x"12";
s_comp_data_b(7 downto 0) <= x"12";
when "001" =>
--when "01" =>
s_comp_data_a(15 downto 8) <= x"34";
s_comp_data_b(15 downto 8) <= x"34";
when "010" =>
--when "10" =>
s_comp_data_a(23 downto 16) <= x"56";
s_comp_data_b(23 downto 16) <= x"56";
when "011" =>
--when "11" =>
s_comp_data_a(31 downto 24) <= x"78";
s_comp_data_b(31 downto 24) <= x"78";
when others =>
null;
end case;
end if;
end if;
end process dpram_dual_clock_b_p;
end Behavioral;
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