这是一个fpga做从机的程序，我是用dsp发送数据，已经可以发送了，可以从示波器看出来，然后fpga能否接收到数据，现在不知道怎么看，求高手帮忙看下这个程序能否实现fpga接受数据，是否可以通过modelsim仿真接受数据呢？求指导，，谢谢。。。上个帖子还没有结，不知道怎么给分，，不好意思！！！
程序如下，注释有的是自己注释的，
module spi_slave (clk,sck,mosi,miso,ssel,led);
input clk;
input sck,mosi;
input ssel;
output miso,led;
//sychronize sck to the fpga clock using a 3-bits shift register
reg[2:0] sckr;
always @ (posedge clk)
sckr <= {sckr[1:0],sck};//来一个时钟就把输入左移一位
wire sck_risingedge = (sckr[2:1]==2'b01);//now we can detect sck rising edges ssel_active=1
wire sck_fallingedge = (sckr[2:1]==2'b10);//and falling edges ssel_active=0
//same thing for ssel
//wire ssel_active = ssel;
reg[2:0] sselr;
always @ (posedge clk)
sselr <={sselr[1:0],ssel};//来一个时钟就把输入左移一位
wire ssel_active =~sselr[1];//~按位取反
wire ssel_startmessage = (sselr[2:1]==2'b10);//message start at falling edge ssel_active=0
wire ssel_endmessage = (sselr[2:1]==2'b01);//message stops at rising edge ssel_active=1
//for MOSI
reg[1:0] mosir;
always @ (posedge clk)
mosir <= {mosir[0],mosi};//不停采样
wire mosi_data = mosir[1];
//always @ (posedge clk)
// wire mosi_data = mosi;
//now receiving data from the spi bus is easy
reg[2:0] bitcnt;// we handle spi in 8-bits format,so need a 3bits counter to count the bits as the come in
reg byte_received;//high when a byte has been received
reg [7:0] byte_data_received;
always @ (posedge clk)
begin
if(~ssel_active) //when上升沿,ssel_active=1
bitcnt <= 3'b000;
else
if(sck_risingedge)//上升沿接收数据
begin
bitcnt <= bitcnt+3'b001;
byte_data_received <={byte_data_received[6:0],mosi_data};//implement a shift-left register(since we receive the data MSB first)
end
end
always @ (posedge clk)
begin
byte_received <= ssel_active &&sck_risingedge&&(bitcnt==3'b111);
end
//we use the LSB of the data received to control an led
reg led;
always @ (posedge clk)
begin
if(byte_received)
led <= byte_data_received[0];
end
//finally the transmission part
reg[7:0] byte_data_sent;
reg[7:0] cnt;
always @ (posedge clk)
if(ssel_startmessage)//下降沿发送数据,//message start at falling edge ssel_active=0
cnt <= cnt+8'h1;//count the messages
always @ (posedge clk)
if(ssel_active)
begin
if(ssel_startmessage)
byte_data_sent <= cnt;//first byte sent in a message is the message count
else
if(sck_fallingedge)
begin
if(bitcnt==3'b000)
byte_data_sent <= 8'h00; //after that,we send 0s
else
byte_data_sent <={byte_data_sent[6:0],1'b0};
end
end
assign miso = byte_data_sent[7];
endmodule |
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