刚开始学CPLD，使用的型号是EPM3256ATC144-7N，编写了一段程序，ledout32的3个引脚没有输出。程序如下：
module kkg(pmaddr,pmd,pmcs1,pmrd,pmwr,clk, jc17,jc18,jc19,jc20,jc21,jc22,jc23,jc24,jc25,jc26,jc27,jc28,jc29,jc30,jc31,jc32, ledout17,ledout18,ledout19,ledout20,ledout21,ledout22,ledout23,ledout24, ledout25,ledout26,ledout27,ledout28,ledout29,ledout30,ledout31,ledout32);
input clk;
input pmcs1;
input pmrd;
input pmwr;
input [7:0] pmaddr;
input[1:0] jc17,jc18,jc19,jc20,jc21,jc22,jc23,jc24,jc25,jc26,jc27,jc28,jc29,jc30,jc31,jc32;
inout [7:0] pmd;
output [2:0] ledout17,ledout18,ledout19,ledout20,ledout21,ledout22,ledout23,ledout24,
ledout25,ledout26,ledout27,ledout28,ledout29,ledout30,ledout31,ledout32;
reg [7:0] status;
reg [7:0] pmd_reg;
reg rdstate;
reg wrstate;
reg [2:0] ledout17,ledout18,ledout19,ledout20,ledout21,ledout22,ledout23,ledout24, ledout25,ledout26,ledout27,ledout28,ledout29,ledout30,ledout31,ledout32;
initial
begin
pmd_reg=8'bzzzzzzzz;
end
always@(posedge clk)
if(!pmcs1)
begin
status<=pmaddr;
case ({pmrd,pmwr})
2'b11:
begin
wrstate=1'b1;
rdstate=1'b1;
end
2'b10:
begin
if((status>8'h10)&&(status<8'h21))
begin
wrstate=1'b0;
rdstate=1'b1;
end
else
begin
wrstate=1'b1;
rdstate=1'b1;
end
end
2'b01:
begin
if((status>8'h30)&&(status<8'h41))
begin
wrstate=1'b1;
rdstate=1'b0;
end
else
begin
wrstate=1'b1;
rdstate=1'b1;
end
end
2'b00:
begin
wrstate=1'b1;
rdstate=1'b1;
end
endcase
end
else
begin
wrstate=1'b1;
rdstate=1'b1;
end
always@(posedge pmwr)
if((wrstate==1'b0)&&(rdstate!=1'b0))
begin
case(status)
8'h20: ledout32 <= pmd[6:4];//**********
8'h1F: ledout31 <= pmd[6:4];
8'h1E: ledout30 <= pmd[6:4];
8'h1D: ledout29 <= pmd[6:4];
8'h1C: ledout28 <= pmd[6:4];
8'h1B: ledout27 <= pmd[6:4];
8'h1A: ledout26 <= pmd[6:4];
8'h19: ledout25 <= pmd[6:4];
8'h18: ledout24 <= pmd[6:4];
8'h17: ledout23 <= pmd[6:4];
8'h16: ledout22 <= pmd[6:4];
8'h15: ledout21 <= pmd[6:4];
8'h14: ledout20 <= pmd[6:4];
8'h13: ledout19 <= pmd[6:4];
8'h12: ledout18 <= pmd[6:4];
8'h01: ledout17 <= pmd[6:4];
endcase
end
always@(posedge clk)
if((rdstate==1'b0)&&(!pmcs1))
begin
case(status)
8'h40: begin
pmd_reg[0]=jc32[0];
//pmd_reg[1]<=0;
pmd_reg[2]=jc32[1];
end
8'h3F: begin
pmd_reg[0]<=jc31[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc31[1];
end
8'h3E: begin
pmd_reg[0]<=jc30[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc30[1];
end
8'h3D: begin
pmd_reg[0]<=jc29[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc29[1];
end
8'h3C: begin
pmd_reg[0]<=jc28[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc28[1];
end
8'h3B: begin
pmd_reg[0]<=jc27[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc27[1];
end
8'h3A: begin
pmd_reg[0]<=jc26[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc26[1];
end
8'h39: begin
pmd_reg[0]<=jc25[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc25[1];
end
8'h38: begin
pmd_reg[0]<=jc24[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc24[1];
end
8'h37: begin
pmd_reg[0]<=jc23[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc23[1];
end
8'h36: begin
pmd_reg[0]<=jc22[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc22[1];
end
8'h35: begin
pmd_reg[0]<=jc21[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc21[1];
end
8'h34: begin
pmd_reg[0]<=jc20[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc20[1];
end
8'h33: begin
pmd_reg[0]<=jc19[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc19[1];
end
8'h32: begin
pmd_reg[0]<=jc18[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc18[1];
end
8'h31: begin
pmd_reg[0]<=jc17[0];
// pmd_reg[1]<=0;
pmd_reg[2]<=jc17[1];
end
endcase
end
assign pmd=((rdstate==1'b0)&&(!pmcs1))?pmd_reg:8'bzzzzzzzz;
endmodule
高手帮忙分析程序有无问题，是不是quartus II 配置不正确，谢谢。 |
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