/*锁相环的设置*/
PLL_Config myConfig = {
0, //IAI: the PLL locks using the same process that was underway
//before the idle mode was entered
1, //IOB: If the PLL indicates a break in the phase lock,
//it switches to its bypass mode and restarts the PLL phase-locking
//sequence
24, //PLL multiply value; multiply 24 times
1 //Divide by 2 PLL divide value; it can be either PLL divide value
//(when PLL is enabled), or Bypass-mode divide value
//(PLL in bypass mode, if PLL multiply value is set to 1)
};
main()
{
int i = 0;
/*初始化CSL库*/
CSL_init();
/*设置系统的运行速度为144MHz*/
PLL_config(&myConfig);
在对数字锁相环的配置中，IOB=1，不是代表时钟发生器工作在旁路模式吗？
那为什么配置PLL MULT=24，PLL DIV=1，采用锁定模式，计算CPU的时钟频率为144MHz？
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