module pwm_f2 (clk,rst,pwm1,pwm2,clk_div);
input rst;
input clk;
output reg pwm1;
output reg pwm2;
output reg clk_div;
reg[19:0]cnt;
always@(posedge clk or negedge rst)
if(!rst) cnt<=20'd0;
else if (cnt<20'd999999)
cnt<=cnt+1'b1;
else cnt<=20'd0;
//////////////////////
reg[19:0]cnt0;
always@(posedge clk or negedge rst)
if(!rst) cnt0<=20'd0;
else if(cnt0<20'd10000)cnt0<=cnt0+1'b1;
else cnt0<=20'd0;
always@(posedge clk or negedge rst)
if(!rst) clk_div<=1'b0;
else if(cnt0==10000)clk_div<=~clk_div;
else clk_div<=clk_div;
//shield the shake and check the posedge and negedge
//pwm1,pwm2
reg[9:0] keyr;
always@(posedge clk or negedge rst)//convention!!!sensitive language, if signal can match the quest after always@,then the language can be compiled
if(!rst) keyr<=4'b1111111111; //when !rst,then the number can be delivered
else keyr<={keyr[8:0],clk_div};//from low number to high
wire key_pos=keyr[0]&~keyr[9];//in the reg[3:0] they are all the key
wire key_neg=~keyr[0]&keyr[9];
reg[1:0] state;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
state=2'b00; // the state that indicate no posedge and also no negedge
end
else
begin
if(key_pos)
begin
state=2'b01; // posedge of pwm_h
end
else if(key_neg)
begin
state=2'b10; // negedge of pwm_h
end
end
end
reg HL;
always@(posedge clk or negedge rst)
if(!rst) HL<=1'b0;
else if(state==2'b01)HL<=1'b1;
else if(state==2'b10)HL<=1'b0;
////////////////////////////////////////////
reg[19:0] dead_cnt;
always@( clk or rst)//posedge negedge
begin
if(!rst)
begin
dead_cnt<=20'd0; //deadtime=Dtime+1'b1;
pwm1<=1;
pwm2<=1;
end
else
begin
if(HL)
begin
if(dead_cnt==200) // if cnt== MAX
begin dead_cnt<=dead_cnt; pwm1<=1'b1;pwm2<=1'b0;end
else
begin dead_cnt<=dead_cnt+1'b1; pwm1<=1'b0;pwm2<=1'b0;end
end
else if(!HL)
begin
if(dead_cnt==0) // if cnt== MIN
begin dead_cnt<=dead_cnt; pwm1<=1'b0;pwm2<=1'b1; end
else
begin dead_cnt<=dead_cnt-1'b1;pwm1<=1'b0;pwm2<=1'b0; end
end
// else
// begin dead_cnt<=dead_cnt; end
/* if(dead_cnt==200) // the lines below this line give the logical of the output pwm
begin
pwm1<=1;
pwm2<=0;
end
else if(dead_cnt==0)
begin
pwm1<=0;
pwm2<=1;
end
else if( (dead_cnt>0) && (dead_cnt<200) )
begin
pwm1<=0;
pwm2<=0;
end */
end
end
endmodule
clk_div有信号输出，但是PWM1和PWM2没有信号输出。恳请知道的朋友解答一下，非常感激 |
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