本帖最后由 cdcc0606 于 2015-1-26 21:19 编辑
我的输入是一个频率可变的方波。然后要求输出是固定脉冲宽度为660us的方波，不管输入频率是多少。我的程序总是会在一段时间过后丢失其中一个输出脉冲，请问这是为什么呢？我的程序如下。library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
--! top_sensors entity declaration
-------------------------------------------------------------------------------
entity top_sensors is
port
(
-- Input ports
reset : in std_logic; --! system clock
clk : in std_logic; --! signal reset
I1 : in std_logic; --! pulse sensor 1
-- Output ports
Top_Tour_T1 : out std_logic --! Top round sensor 1 output is fixed for 660us
);
end entity top_sensors;
-------------------------------------------------------------------------------
--! top_sensors architecture declaration
-------------------------------------------------------------------------------
architecture behavior of top_sensors is
signal flag1: integer RANGE 0 TO 2:=0; --! verify the end of the 660us top1
signal cpt1: integer RANGE 0 TO 33000:=0; --! 660us=> 660/0.02us=33000: counter clk FPGA=33000
begin
----------------------------------------------------------------------------
--! [url=home.php?mod=space&uid=247401]@brief[/url] generate top round for each sensor
--! @detail each top is fixed for 660us
----------------------------------------------------------------------------
process(clk, reset)
begin
if reset='0' then
Top_Tour_T1 <= '0';
cpt1<=0;
elsif rising_edge(clk)then
--if I1=0=>I1=1
if(I1='1')and (cpt1=0)then
Top_Tour_T1<='1';
cpt1<=1;
end if;
--begin the counter 330000 pour 660us
if(cpt1>0)and (cpt1<33000)then
cpt1<=cpt1+1;
if(I1='0')then
elsif(I1='1')and (flag1=1)then
cpt1<=0;
Top_Tour_T1<='0';
flag1<=0;
end if;
--after 660us, top disappear
end if;
if(cpt1=33000)then
if(I1='0')then
cpt1<=0;
end if;
Top_Tour_T1<='0';
end if;
end if;
end process;
end architecture behavior;
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