本帖最后由 Othink 于 2015-5-14 22:35 编辑
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#include "math.h"
//===========================================================================
#define SYSTEM_CLK 150000000 //cpu frequency
#define Dead_Time 800 //dead time
#define PI 3.1415926 //pi value
//===========================================================================
Uint16 CarryRatio=160; // carries ratio
float xn=0.0000;
Uint16 temp=0;
float ModRatio=0.6; //modlation ratio
Uint16 EpwmDiv=2; //epwm clock dive rate
float F_Out=50.0; //frequency of output
//===========================================================================
interrupt void Epwm1int_isr(void); //epwm1 interrupt
interrupt void Epwm2int_isr(void); //epwm2 interrupt
interrupt void Epwm3int_isr(void); //epwm3 interrupt
void Epwm1Setup(void);
void Epwm2Setup(void);
void Epwm3Setup(void);
//===========================================================================
void main(void){
// Step 1. Initialize System Control:
InitSysCtrl();
// Step 2. Initalize GPIO:
InitGpio(); // Skipped for this example
InitXintf16Gpio(); //zq
// Step 3. Clear all interrupts and initialize PIE vector table:
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &Epwm1int_isr;
PieVectTable.EPWM2_INT = &Epwm2int_isr;
PieVectTable.EPWM3_INT = &Epwm3int_isr;
Epwm1Setup();
Epwm2Setup();
Epwm3Setup();
EPwm1Regs.TBCTR=0;
EPwm1Regs.TBCTL.bit.SWFSYNC=1; // generate a soft synch
EDIS; // This is needed to disable write to EALLOW protected registers
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
//enable core interrupt enable register : group 3 is enabled
IER |= M_INT3;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
InitEPwmGpio();
for(; 1;)
{
}
}
//===========================================================================
void Epwm1Setup(void){
//Time base configuration
EPwm1Regs.TBPRD=(SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1;
EPwm1Regs.TBPHS.half.TBPHS=0; //phase equal 0
EPwm1Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN; //UpDownMoudle
if(EpwmDiv==1)EPwm1Regs.TBCTL.bit.HSPCLKDIV=0;
else EPwm1Regs.TBCTL.bit.HSPCLKDIV=EpwmDiv/2;
EPwm1Regs.TBCTL.bit.PRDLD=TB_SHADOW; // shadow the accesses register TBPRD the to read or write
EPwm1Regs.TBCTL.bit.FREE_SOFT=3; //time basic run free
EPwm1Regs.TBCTL.bit.PHSDIR=1;//count up after a syncy
EPwm1Regs.TBCTL.bit.PHSEN=1; //
EPwm1Regs.TBCTL.bit.SYNCOSEL=TB_CTR_ZERO; //master
EPwm1Regs.TBCTR=0;
//compare register configuration
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
//EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
//EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;
EPwm1Regs.CMPA.half.CMPA=(Uint16)((sin((xn/CarryRatio)*2*PI)*ModRatio+0.5)*((SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1));
//action qualifier configuration
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
//EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;
//EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
//dead band register configuration
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = Dead_Time;
EPwm1Regs.DBFED = Dead_Time;
//trip zone register configuration
//event trigger register configuration
EPwm1Regs.ETSEL.bit.INTSEL = 1;
EPwm1Regs.ETSEL.bit.INTEN = 1;
EPwm1Regs.ETPS.bit.INTPRD = 1;
EPwm1Regs.ETCLR.bit.INT = 1;
}
void Epwm2Setup(void){
//Time base configuration
EPwm2Regs.TBPRD=(SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1;
EPwm2Regs.TBPHS.half.TBPHS=0; //phase equal 0
EPwm2Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN; //UpDownMoudle
if(EpwmDiv==1)EPwm2Regs.TBCTL.bit.HSPCLKDIV=0;
else EPwm2Regs.TBCTL.bit.HSPCLKDIV=EpwmDiv/2;
EPwm2Regs.TBCTL.bit.PRDLD=TB_SHADOW; // shadow the accesses register TBPRD the to read or write
EPwm2Regs.TBCTL.bit.FREE_SOFT=3; //time basic run free
EPwm2Regs.TBCTL.bit.PHSDIR=1;//count up after a syncy
EPwm2Regs.TBCTL.bit.PHSEN=1; //
EPwm2Regs.TBCTL.bit.SYNCOSEL=TB_SYNC_IN; //master
EPwm2Regs.TBCTR=0;
//compare register configuration
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
//EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
//EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;
EPwm2Regs.CMPA.half.CMPA=(Uint16)((sin((xn/CarryRatio+0.1/0.3)*2*PI)*ModRatio+0.5)*((SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1));
//action qualifier configuration
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
//EPwm2Regs.AQCTLB.bit.CAU = AQ_SET;
//EPwm2Regs.AQCTLB.bit.CAD = AQ_CLEAR;
//dead band register configuration
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = Dead_Time;
EPwm2Regs.DBFED = Dead_Time;
//trip zone register configuration
//event trigger register configuration
EPwm2Regs.ETSEL.bit.INTSEL = 1;
EPwm2Regs.ETSEL.bit.INTEN = 1;
EPwm2Regs.ETPS.bit.INTPRD = 1;
EPwm2Regs.ETCLR.bit.INT = 1;
}
void Epwm3Setup(void){
//Time base configuration
EPwm3Regs.TBPRD=(SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1;
EPwm3Regs.TBPHS.half.TBPHS=0; //phase equal 0
EPwm3Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN;
if(EpwmDiv==1)EPwm3Regs.TBCTL.bit.HSPCLKDIV=0;
else EPwm3Regs.TBCTL.bit.HSPCLKDIV=EpwmDiv/2; //UpDownMoudle
EPwm3Regs.TBCTL.bit.PRDLD=TB_SHADOW; // shadow the accesses register TBPRD the to read or write
EPwm3Regs.TBCTL.bit.FREE_SOFT=3; //time basic run free
EPwm3Regs.TBCTL.bit.PHSDIR=1;//count up after a syncy
EPwm3Regs.TBCTL.bit.PHSEN=1;
EPwm3Regs.TBCTL.bit.SYNCOSEL=TB_SYNC_IN; //slave
EPwm3Regs.TBCTR=0;
//compare register configuration
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
//EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
//EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;
EPwm3Regs.CMPA.half.CMPA=(Uint16)((sin((xn/CarryRatio+0.2/0.3)*2*PI)*ModRatio+0.5)*((SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1));
//action qualifier configuration
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
//EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;
//EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
//dead band register configuration
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED = Dead_Time;
EPwm3Regs.DBFED = Dead_Time;
//trip zone register configuration
//event trigger register configuration
EPwm3Regs.ETSEL.bit.INTSEL = 1;
EPwm3Regs.ETSEL.bit.INTEN = 1;
EPwm3Regs.ETPS.bit.INTPRD = 1;
EPwm3Regs.ETCLR.bit.INT = 1;
}
//===========================================================================
interrupt void Epwm1int_isr(void){ //epwm1 interrupt
EALLOW;
EPwm1Regs.ETCLR.bit.INT = 1;
EDIS;
xn++;
if(xn==CarryRatio)xn=0;
EPwm1Regs.CMPA.half.CMPA=(Uint16)((sin((xn/CarryRatio)*2*PI)*ModRatio+0.5)*((SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1));
//enable other interrupt get be done in group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
interrupt void Epwm2int_isr(void){ //epwm2 interrupt
EALLOW;
EPwm2Regs.ETCLR.bit.INT = 1;
EDIS;
EPwm2Regs.CMPA.half.CMPA=(Uint16)((sin((xn/CarryRatio+0.1/0.3)*2*PI)*ModRatio+0.5)*((SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1));
//enable other interrupt get be done in group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
interrupt void Epwm3int_isr(void){ //epwm3 interrupt
EALLOW;
EPwm3Regs.ETCLR.bit.INT = 1;
EDIS;
EPwm3Regs.CMPA.half.CMPA=(Uint16)((sin((xn/CarryRatio+0.2/0.3)*2*PI)*ModRatio+0.5)*((SYSTEM_CLK/EpwmDiv)/(CarryRatio*F_Out*2)+1));
//enable other interrupt get be done in group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//===========================================================================
// No more.
//===========================================================================
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