刚学习DSP，写了一个DSP定时器中断的代码，总是不能响应定时中断，请大侠指点，主要代码如下，功能就是每次定时器中断时，收发一次传过来的声音。
/*SEEDDM642的emifa的设置结构*/
EMIFA_Config Seeddm642ConfigA ={
0x00052078,/*gblctl EMIFA(B)global control register value */
/*将CLK6、4、1使能；将MRMODE置1；使能EK2EN,EK2RATE*/
0xffffffd3,/*cectl0 CE0 space control register value*/
/*将CE0空间设为SDRAM*/
0x73a28e01,/*cectl1 CE1 space control register value*/
/*Read hold: 1 clock;
MTYPE : 0000,选择8位的异步接口
Read strobe ：001110；14个clock宽度
TA：2 clock; Read setup 2 clock;
Write hold :2 clock; Write strobe: 14 clock
Write setup :7 clock
-- ---------------
\ 14c /1c
\----------------/ */
0x22a28a22, /*cectl2 CE2 space control register value*/
0x22a28a42, /*cectl3 CE3 space control register value*/
0x57115000, /*sdctl SDRAM control register value*/
0x0000081b, /*sdtim SDRAM timing register value*/
0x001faf4d, /*sdext SDRAM extension register value*/
0x00000002, /*cesec0 CE0 space secondary control register value*/
0x00000002, /*cesec1 CE1 space secondary control register value*/
0x00000002, /*cesec2 CE2 space secondary control register value*/
0x00000073 /*cesec3 CE3 space secondary control register value*/
};
/********************************************************************//*设置定时中断采集，SEEDDM642的Timer0的设置结构*/
TIMER_Config MyConfig = {
0x00000200, /* ctl */
0x002124f8, /* prd,CPU主频为600MHz，即内部时钟源为75MHz，则定时周期为1ms */
0x00000000 /* cnt */
};
/********************************************************************/
/*SEEDDM642的IIC的设置结构*/
I2C_Config SEEDDM642IIC_Config = {
0, /* master mode, i2coar;采用主模式 */
0, /* no interrupt, i2cimr;只写，不读，采用无中断方式*/
(20-5), /* scl low time, i2cclkl; */
(20-5), /* scl high time,i2cclkh; */
1, /* configure later, i2ccnt;*/
0, /* configure later, i2csar;*/
0x4ea0, /* master tx mode, */
/* i2c runs free, */
/* 8-bit data + NACK */
/* no repeat mode */
(75-1), /* 4MHz clock, i2cpsc */
};
CHIP_Config SEEDDM642percfg = {
CHIP_VP2+\
CHIP_VP1+\
CHIP_VP0+\
CHIP_I2C+\
CHIP_MCASP0
};
I2C_Handle hSeeddm642i2c;
/*设置需打开的音频的句柄*/
SEEDDM642_AIC23_Handle dm642aic23handle0,dm642aic23handle1;
SEEDDM642_AIC23_Handle dm642aic23handle2,dm642aic23handle3;
/* Internal codec state used to simulate read/write functionality */
SEEDDM642_AIC23_Config codecstate = SEEDDM642_AIC23_DEFAULTCONFIG;
MCASP_Handle SEEDdm642codec;
extern far void vectors();
/*此程序可将四个采集口的数据经过Video Port0送出*/
void main()
{
/*-------------------------------------------------------*/
/* perform all initializations */
/*-------------------------------------------------------*/
TIMER_Handle hTimer;
Uint32 dwTimerEventId;
/*定时器启动*/
hTimer = TIMER_open(TIMER_DEV0, TIMER_OPEN_RESET);
dwTimerEventId = TIMER_getEventId(hTimer);
TIMER_config(hTimer, &MyConfig);
TIMER_start(hTimer); //定时中断，间隔为1ms
/*----------------------------------------------------------*/
/*Initialise CSL，初始化CSL库*/
CSL_init();
CHIP_config(&SEEDDM642percfg);
/*----------------------------------------------------------*/
/*EMIFA的初始化，将CE0设为SDRAM空间，CE1设为异步空间
注，DM642支持的是EMIFA，而非EMIF*/
EMIFA_config(&Seeddm642ConfigA);
/*----------------------------------------------------------*/
/*中断向量表的初始化*/
//Point to the IRQ vector table
IRQ_setVecs(vectors);
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_map(dwTimerEventId, 4); //定时器0中断事件重新映射到4，即可屏蔽中断的最优先级， MUXH[25:21]=0×02
IRQ_reset(dwTimerEventId);
IRQ_enable(dwTimerEventId);
IRQ_map(IRQ_EVT_VINT1, 11); //EMU实时数据交换（RTDX）映射到11 MUXH[9:5]=0x0a
IRQ_reset(IRQ_EVT_VINT0);
IRQ_enable(IRQ_EVT_VINT0);
IRQ_map(IRQ_EVT_VINT0, 12); //EMU RTDX 发送 映射到12 MUXH[14:10]=0x0b
IRQ_reset(IRQ_EVT_VINT1);
IRQ_enable(IRQ_EVT_VINT1);
/*----------------------------------------------------------*/
/*AIC23B的初始化*/
hSeeddm642i2c = I2C_open(I2C_PORT0,I2C_OPEN_RESET);
I2C_config(hSeeddm642i2c,&SEEDDM642IIC_Config);
/*第一通路AIC23工作在主模式*/
// codecstate.regs[SEEDDM642_AIC23_DIGIF] = 0x13;
dm642aic23handle0 = EVMDM642_AIC23_open(hSeeddm642i2c,0,&codecstate);
/*----------------------------------------------------------*/
/*MCASP的初始化*/
SEEDdm642codec = SEEDDM642_AIC23_openCodec();
/*----------------------------------------------------------*/
/*音频的采集与回放*/
for(;;)
{
}
}
interrupt void timer0(void)
{
Uint32 codecdata;
if(MCASP_FGETH(SEEDdm642codec,RSTAT,RDATA))
{
codecdata= MCASP_RGETH(SEEDdm642codec,RBUF1);
MCASP_RSETH(SEEDdm642codec,XBUF0,codecdata);
}
else
{
asm(" nop");
}
IRQ_clear(TIMER_DEV0);
} |
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