就找到一个相关的寄存器如下,也没什么帮助好像!! $27 LVD O/S2 O/S1 O/S0 R/W Bit0: PORTD as LCD SEG1 - 4 control register Bit1: PORTE as LCD SEG5 - 8 control register Bit2: LCD SEG9 - 28 as output control register Bit3: LCD Voltage degrade control register
When LVD is set to 1 and the divider resistance is 270k, LCD voltage power will be degraded to about 90% of VDD. It is designed to reduce extra LCD contrast control output pins. Then the LCD can be fitted automatically for different voltage levels by the software.
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