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我写了一段代码，主要实现的是状态机各个状态之间的相互转化<br /><br />这段代码在quartusII5.0下编译成功且下载到板子了后用signaTapII调试的结果完全正确<br /><br />可是用QuartusII6.0编译后出现Warning：case item is ignored......blala......<br /><br />网上给出来的信息说：<br /><br />CAUSE: In a Case Statement at the specified location in a Verilog Design File (.v), you specified a case item expression that has more significant bits than the number of bits in the case expression that it is being compared against. As a result, the case item expression can never apply, and is ignored by the Quartus II software<br /><br />仔细思考后觉得应该是我的状态机中的状态编码有问题：<br /><br />我原来用的是自然数编码，<br /><br />也IDLE=0，STATE1=1,STATE2=2,STATE3=3,STATE4=4....<br /><br />然后把状态编码改写成：<br /><br />IDLE=0,STATE1=1,STATE2=2,STATE3=4，STATE4=8.....<br /><br />编译的结果显示这个Warning消失了。<br /><br />以后对状态机的编码要小心了<br /> |
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