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ARCHITECTURE BEHV OF GATE_SIGNAL IS<br />SIGNAL COUNT: INTEGER RANGE 0 TO 93:=0;<br />SIGNAL RST: STD_LOGIC;<br />BEGIN <br /> PROCESS(CLK,X1_X10_X100HZ,X1K_X10K_X100KHZ)<br /> BEGIN <br /> IF CLK'EVENT AND CLK='1' THEN<br /> IF X1_X10_X100HZ='1' THEN <br /> IF COUNT=93 THEN COUNT<=0;RST<='0';<br /> ELSE IF COUNT=50 THEN RST<='1';<br /> END IF;<br /> END IF;<br /> END IF;<br /> ELSE IF X1K_X10K_X100KHZ='1' THEN <br /> IF COUNT=18 THEN COUNT<=0;RST<='0';<br /> ELSE IF COUNT=9 THEN RST<='1';<br /> END IF;<br /> END IF;<br /> END IF; <br /> END IF;<br /> COUNT<=COUNT+1;<br /> END PROCESS;<br /> RESET<=RST;<br />END BEHV;<br />编译时出现错误如下：<br />Error (10483): VHDL error at GATE_SIGNAL.vhd(17): can't infer register for signal "COUNT[0]" because signal does not hold its value outside clock edge！<br />是不是信号不能重复幅值？我想让输出的频率能够选择。<br />麻烦帮忙看下！ 多谢！ |
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