|
我是想用McBSP接收一个帧信号为8K，时钟为4.096M的2倍E1的信号。<br />想法是帧信号和时钟都由外部提供，每帧64个8比特数据，A-law压扩。<br /><br />DMA设置为64个元素，接收/发送完64个数据产生中断。<br /><br />我搞了好几天还是不行。<br />似乎是串口没有配置对，明明配置成一帧64个元素，用rrdy/xrdy来触发中断，结果一帧只来了一个中断，也就是说只收到一个数据，其它63个都没有了？不知道怎么回事。<br />我的DMA也一直工作不正常，中断只能进去一次，后面就进不去了。<br />现在天天找问题，头晕脑胀啊。<br /><br />我的配置文件放在下面大家看看。<br />因为怕那个8k的时钟对不齐，所以先初始化一个由FRAME触发的中断，然后在这个中断程序里面重新初始化串口和DMA。<br />发现5502真是很麻烦。<br /><br /><br /><br /><br />/********************************************************************************/<br />/* 文件名: GSBPerConfg.h */ <br />/* 创建日期: 08/06/2007 */<br />/* 功能描述: 外设寄存器配置参数 */<br />/* Author ： whj */<br />/********************************************************************************/<br />#ifndef _GSB_PER_CNFG<br />#define _GSB_PER_CNFG<br /><br />#include <csl.h><br />#include <csl_pll.h><br />#include <csl_chip.h><br />#include <csl_irq.h><br />#include <csl_gpt.h><br /><br />#include <csl_chip.h><br />#include <csl_mcbsp.h><br />#include <csl_hpi.h><br />#include <csl_dma.h><br /><br /><br />//一帧中的时隙数<br />#define TS 64<br /><br /><br />/* Define transmit and receive buffers */<br />#pragma DATA_SECTION(xmt,"dmaMem")<br />Int16 xmt[TS];<br /><br />#pragma DATA_SECTION(rcv,"dmaMem")<br />Int16 rcv[TS];<br /><br /><br /><br /><br /> /*64 bit general purpose timer */<br /> /* Define and initialize the GPT module configuration structure */<br /> GPT_Config MyGptConfig = {<br /> 0, //Emulation management register<br /> 0, //GPIO interrupt control register<br /> 0, //GPIO enable register<br /> 0, //GPIO direction register<br /> 0, //GPIO data register<br /> 0xB9EF, //Timer period register 1<br /> 0x05F5, //Timer period register 2<br /> 0, //Timer period register 3<br /> 0, //Timer period register 4<br /> GPT_GPTCTL1_RMK( //Timer control register 1<br /> GPT_GPTCTL1_TIEN_NOT_GATED,<br /> GPT_GPTCTL1_CLKSRC_VBUS,<br /> GPT_GPTCTL1_ENAMODE_CONTINUOUS,<br /> GPT_GPTCTL1_PWID_INACTIVE_1CYCLE,<br /> GPT_GPTCTL1_CP_CLOCK_MODE,<br /> GPT_GPTCTL1_INVIN_DONT_INVERT_OUTPUT,<br /> GPT_GPTCTL1_INVOUT_DONT_INVERT_OUTPUT<br /> ), <br /> GPT_GPTCTL2_RMK( //Timer control register 2<br /> GPT_GPTCTL2_TIEN_NOT_GATED,<br /> GPT_GPTCTL2_CLKSRC_VBUS,<br /> GPT_GPTCTL2_ENAMODE_CONTINUOUS,<br /> GPT_GPTCTL2_PWID_INACTIVE_1CYCLE,<br /> GPT_GPTCTL2_CP_CLOCK_MODE,<br /> GPT_GPTCTL2_INVIN_DONT_INVERT_OUTPUT,<br /> GPT_GPTCTL2_INVOUT_DONT_INVERT_OUTPUT<br /> ), <br /> GPT_GPTGCTL1_RMK( //Global timer control register<br /> GPT_GPTGCTL1_PSC34_DEFAULT,<br /> GPT_GPTGCTL1_TIMMODE_DEFAULT,<br /> GPT_GPTGCTL1_TIM34RS_NOT_IN_RESET,<br /> GPT_GPTGCTL1_TIM12RS_NOT_IN_RESET<br /> ) <br /> };<br /><br />/********** McBSP Config *****************/<br /> MCBSP_Config GSBMcBspConfigInit = {<br /> MCBSP_SPCR1_RMK(<br /> MCBSP_SPCR1_DLB_OFF, /* Digital loopback Disable */<br /> MCBSP_SPCR1_RJUST_RZF, /* Right justify the data and zero fill the MSBs. */<br /> MCBSP_SPCR1_CLKSTP_DISABLE, /*Clock stop mode is disabled. only used in SPI protocol */<br /> MCBSP_SPCR1_DXENA_OFF, /*DX delay enabler off */ <br /> MCBSP_SPCR1_ABIS_DISABLE, /* */<br /> MCBSP_SPCR1_RINTM_FRM, /* Receive Ready interrupt*/<br /> MCBSP_SPCR1_RSYNCERR_NO, /* No error */<br /> MCBSP_SPCR1_RFULL_YES, /* Read Only */<br /> MCBSP_SPCR1_RRDY_YES, /* Read Only */<br /> MCBSP_SPCR1_RRST_ENABLE /* Not in Reset */<br /> ),<br /> //0x01,<br /> MCBSP_SPCR2_RMK(<br /> MCBSP_SPCR2_FREE_NO, /*The McBSP transmit and receive clocks are affected as determined by the */<br /> /*SOFT bit. */<br /> MCBSP_SPCR2_SOFT_YES, /* The McBSP transmit clock stops after completion of the current<br /> serial word transfer. The McBSP receive clock is not affected.*/<br /> MCBSP_SPCR2_FRST_FSG, /* 1: frame-sync logic not in Reset*/<br /> MCBSP_SPCR2_GRST_CLKG, /* 1: Not in reset */<br /> MCBSP_SPCR2_XINTM_XRDY, /* interrupt is sent when each one word is tansmitted completely*/<br /> MCBSP_SPCR2_XSYNCERR_NO,<br /> MCBSP_SPCR2_XEMPTY_YES, /*Read Only */<br /> MCBSP_SPCR2_XRDY_YES, /*Read Only */<br /> MCBSP_SPCR2_XRST_ENABLE /* enable transmitter */<br /> ),<br /> MCBSP_RCR1_RMK(<br /> MCBSP_RCR1_RFRLEN1_OF(1), /* 1 words per receive frame */<br /> MCBSP_RCR1_RWDLEN1_8BIT /* receive word length 8 bit */<br /> ),<br /> MCBSP_RCR2_RMK(<br /> MCBSP_RCR2_RPHASE_SINGLE, /* signle phase */ <br /> MCBSP_RCR2_RFRLEN2_OF(0), /* phase 2 not used */<br /> MCBSP_RCR2_RWDLEN2_8BIT , /* no meaning */<br /> MCBSP_RCR2_RCOMPAND_ALAW, /*ALAW companding in reception */<br /> MCBSP_RCR2_RFIG_YES, /* An unexpected FSR pulse causes the receiver to */<br /> /* discard the contents of RSR[1,2] in favor of the new incoming data.*/<br /> MCBSP_RCR2_RDATDLY_1BIT /* rcv 1 bit delay */<br /> ),<br /> MCBSP_XCR1_RMK(<br /> MCBSP_XCR1_XFRLEN1_OF(1), /* Transmit frame length 1 (1 to 128 words). 64 words per frame */<br /> MCBSP_XCR1_XWDLEN1_8BIT /* transmit word length1 8 bit */<br /> ),<br /> MCBSP_XCR2_RMK(<br /> MCBSP_XCR2_XPHASE_SINGLE, /* The transmit frame has only one phase, phase 1 */ <br /> MCBSP_XCR2_XFRLEN2_OF(0), /* phase 2 not used */<br /> MCBSP_XCR2_XWDLEN2_8BIT, /* Transmit word length 2, no used */<br /> MCBSP_XCR2_XCOMPAND_ALAW, /* ALAW companding in transmission */<br /> MCBSP_XCR2_XFIG_YES, /* Unexpected Transmit Frame-Synch Pulse */<br /> MCBSP_XCR2_XDATDLY_1BIT /* xmt 1 bit delay */<br /> ),<br /> MCBSP_SRGR1_RMK(<br /> MCBSP_SRGR1_FWID_OF(0), /* Frame-sync(FSG) pulse width is 1(0+1) CLKG cycles */<br /> MCBSP_SRGR1_CLKGDV_OF(0) /* CLKG frequency = (Input clock frequency) / (CLKGDV + 1), CLKG equals to CLKR/CLKX */<br /> ),<br /> MCBSP_SRGR2_RMK(<br /> MCBSP_SRGR2_GSYNC_FREE, /* Always write 0 to this bit on 5502,NO this function on 5502 */<br /> MCBSP_SRGR2_CLKSP_RISING, /* we don't use CLKS input, don't care this bit*/<br /> MCBSP_SRGR2_CLKSM_CLKS,/* 0 : input clock for sample rate generator is Signal on CLKS/CLKR pin,depend on SCLKME */<br /> MCBSP_SRGR2_FSGM_FSG, /* the transmitter uses frame-sync pulses generated by the sample rate generator */<br /> MCBSP_SRGR2_FPER_OF(511) /* Frame-sync period is 512 CLKG cycles*/ <br /> ),<br /> MCBSP_MCR1_DEFAULT, /* we don't use multiple channels*/<br /> MCBSP_MCR2_DEFAULT,<br /> <br /> MCBSP_PCR_RMK(<br /> 0, /* IDLEEN, 5502 should write to 0*/<br /> MCBSP_PCR_XIOEN_SP, /*The CLKX, FSX, DX, and CLKS pins are serial port pins*/<br /> MCBSP_PCR_RIOEN_SP, /*The CLKR, FSR, DR, and CLKS pins are serial port pins*/<br /> MCBSP_PCR_FSXM_EXTERNAL, /*Transmit frame synchronization is supplied by an external source via the FSX pin.*/<br /> MCBSP_PCR_FSRM_EXTERNAL, /*Receive frame synchronization is supplied by an external source via the FSR pin*/<br /> <br /> MCBSP_PCR_SCLKME_BCLK, /*1 :The input clock for the sample rate generator is taken from the CLKR pin */<br /> /*cause the value of the CLKSM bit of SRGR2 is 0 */<br /> MCBSP_PCR_CLKSSTAT_0, /* CLKS pin status bit. 5502 doesn't have this pin */<br /> MCBSP_PCR_DXSTAT_0, /* DX pin status bit. */<br /> MCBSP_PCR_DRSTAT_0, /* DR pin status bit. Not GPIO, no meaning here */<br /> MCBSP_PCR_CLKXM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKX pin. */<br /> MCBSP_PCR_CLKRM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKR pin. */<br /> MCBSP_PCR_FSXP_ACTIVEHIGH, /* Transmit frame-sync pulses are active low. */<br /> MCBSP_PCR_FSRP_ACTIVEHIGH, /* Receive frame-sync pulses are active low. */<br /> MCBSP_PCR_CLKXP_RISING, /* Transmit data is driven on the rising edge of CLKX，发送上升沿 */<br /> MCBSP_PCR_CLKRP_FALLING /* When the CLKR pin is configured as an input, the external CLKR is not */<br /> /* inverted before being used internally and the receive data is sampled on the */<br /> /* falling edge of CLKR. */<br /> ),<br /> MCBSP_RCERA_DEFAULT, <br /> MCBSP_RCERB_DEFAULT, <br /> MCBSP_RCERC_DEFAULT, <br /> MCBSP_RCERD_DEFAULT, <br /> MCBSP_RCERE_DEFAULT, <br /> MCBSP_RCERF_DEFAULT, <br /> MCBSP_RCERG_DEFAULT, <br /> MCBSP_RCERH_DEFAULT, <br /> MCBSP_XCERA_DEFAULT,<br /> MCBSP_XCERB_DEFAULT,<br /> MCBSP_XCERC_DEFAULT,<br /> MCBSP_XCERD_DEFAULT, <br /> MCBSP_XCERE_DEFAULT,<br /> MCBSP_XCERF_DEFAULT, <br /> MCBSP_XCERG_DEFAULT,<br /> MCBSP_XCERH_DEFAULT <br /> };<br /><br /> /********** McBSP Config *****************/<br /> MCBSP_Config GSBMcBspConfig = {<br />// MCBSP_SPCR1_RMK(<br />// MCBSP_SPCR1_DLB_OFF, /* Digital loopback Disable */<br />// MCBSP_SPCR1_RJUST_RZF, /* Right justify the data and zero fill the MSBs. */<br />// MCBSP_SPCR1_CLKSTP_DISABLE, /*Clock stop mode is disabled. only used in SPI protocol */<br />// MCBSP_SPCR1_DXENA_OFF, /*DX delay enabler off */ <br />// MCBSP_SPCR1_ABIS_DISABLE, /* */<br />// MCBSP_SPCR1_RINTM_RRDY, /* Receive Ready interrupt*/<br />// MCBSP_SPCR1_RSYNCERR_NO, /* No error */<br />// MCBSP_SPCR1_RFULL_YES, /* Read Only */<br />// MCBSP_SPCR1_RRDY_YES, /* Read Only */<br />// MCBSP_SPCR1_RRST_ENABLE /* Not in Reset */<br />// ),<br /> 0x01,<br /> MCBSP_SPCR2_RMK(<br /> MCBSP_SPCR2_FREE_NO, /*The McBSP transmit and receive clocks are affected as determined by the */<br /> /*SOFT bit. */<br /> MCBSP_SPCR2_SOFT_YES, /* The McBSP transmit clock stops after completion of the current<br /> serial word transfer. The McBSP receive clock is not affected.*/<br /> MCBSP_SPCR2_FRST_FSG, /* 1: frame-sync logic not in Reset*/<br /> MCBSP_SPCR2_GRST_CLKG, /* 1: Not in reset */<br /> MCBSP_SPCR2_XINTM_XRDY, /* interrupt is sent when each one word is tansmitted completely*/<br /> MCBSP_SPCR2_XSYNCERR_NO,<br /> MCBSP_SPCR2_XEMPTY_YES, /*Read Only */<br /> MCBSP_SPCR2_XRDY_YES, /*Read Only */<br /> MCBSP_SPCR2_XRST_ENABLE /* enable transmitter */<br /> ),<br /> MCBSP_RCR1_RMK(<br /> MCBSP_RCR1_RFRLEN1_OF(TS), /* 64 words per receive frame */<br /> MCBSP_RCR1_RWDLEN1_8BIT /* receive word length 8 bit */<br /> ),<br /> MCBSP_RCR2_RMK(<br /> MCBSP_RCR2_RPHASE_SINGLE, /* signle phase */ <br /> MCBSP_RCR2_RFRLEN2_OF(0), /* phase 2 not used */<br /> MCBSP_RCR2_RWDLEN2_8BIT , /* no meaning */<br /> MCBSP_RCR2_RCOMPAND_ALAW, /*ALAW companding in reception */<br /> MCBSP_RCR2_RFIG_YES, /* An unexpected FSR pulse causes the receiver to */<br /> /* discard the contents of RSR[1,2] in favor of the new incoming data.*/<br /> MCBSP_RCR2_RDATDLY_1BIT /* rcv 1 bit delay */<br /> ),<br /> MCBSP_XCR1_RMK(<br /> MCBSP_XCR1_XFRLEN1_OF(TS), /* Transmit frame length 1 (1 to 128 words). 64 words per frame */<br /> MCBSP_XCR1_XWDLEN1_8BIT /* transmit word length1 8 bit */<br /> ),<br /> MCBSP_XCR2_RMK(<br /> MCBSP_XCR2_XPHASE_SINGLE, /* The transmit frame has only one phase, phase 1 */ <br /> MCBSP_XCR2_XFRLEN2_OF(0), /* phase 2 not used */<br /> MCBSP_XCR2_XWDLEN2_8BIT, /* Transmit word length 2, no used */<br /> MCBSP_XCR2_XCOMPAND_ALAW, /* ALAW companding in transmission */<br /> MCBSP_XCR2_XFIG_YES, /* Unexpected Transmit Frame-Synch Pulse */<br /> MCBSP_XCR2_XDATDLY_1BIT /* xmt 1 bit delay */<br /> ),<br /> MCBSP_SRGR1_RMK(<br /> MCBSP_SRGR1_FWID_OF(0), /* Frame-sync(FSG) pulse width is 1(0+1) CLKG cycles */<br /> MCBSP_SRGR1_CLKGDV_OF(0) /* CLKG frequency = (Input clock frequency) / (CLKGDV + 1), CLKG equals to CLKR/CLKX */<br /> ),<br /> MCBSP_SRGR2_RMK(<br /> MCBSP_SRGR2_GSYNC_FREE, /* Always write 0 to this bit on 5502,NO this function on 5502 */<br /> MCBSP_SRGR2_CLKSP_RISING, /* we don't use CLKS input, don't care this bit*/<br /> MCBSP_SRGR2_CLKSM_CLKS,/* 0 : input clock for sample rate generator is Signal on CLKS/CLKR pin,depend on SCLKME */<br /> MCBSP_SRGR2_FSGM_FSG, /* the transmitter uses frame-sync pulses generated by the sample rate generator */<br /> MCBSP_SRGR2_FPER_OF(511) /* Frame-sync period is 512 CLKG cycles*/ <br /> ),<br /> MCBSP_MCR1_DEFAULT, /* we don't use multiple channels*/<br /> MCBSP_MCR2_DEFAULT,<br /> <br /> MCBSP_PCR_RMK(<br /> 0, /* IDLEEN, 5502 should write to 0*/<br /> MCBSP_PCR_XIOEN_SP, /*The CLKX, FSX, DX, and CLKS pins are serial port pins*/<br /> MCBSP_PCR_RIOEN_SP, /*The CLKR, FSR, DR, and CLKS pins are serial port pins*/<br /> MCBSP_PCR_FSXM_EXTERNAL, /*Transmit frame synchronization is supplied by an external source via the FSX pin.*/<br /> MCBSP_PCR_FSRM_EXTERNAL, /*Receive frame synchronization is supplied by an external source via the FSR pin*/<br /> <br /> MCBSP_PCR_SCLKME_BCLK, /*1 :The input clock for the sample rate generator is taken from the CLKR pin */<br /> /*cause the value of the CLKSM bit of SRGR2 is 0 */<br /> MCBSP_PCR_CLKSSTAT_0, /* CLKS pin status bit. 5502 doesn't have this pin */<br /> MCBSP_PCR_DXSTAT_0, /* DX pin status bit. */<br /> MCBSP_PCR_DRSTAT_0, /* DR pin status bit. Not GPIO, no meaning here */<br /> MCBSP_PCR_CLKXM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKX pin. */<br /> MCBSP_PCR_CLKRM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKR pin. */<br /> MCBSP_PCR_FSXP_ACTIVEHIGH, /* Transmit frame-sync pulses are active low. */<br /> MCBSP_PCR_FSRP_ACTIVEHIGH, /* Receive frame-sync pulses are active low. */<br /> MCBSP_PCR_CLKXP_RISING, /* Transmit data is driven on the rising edge of CLKX，发送上升沿 */<br /> MCBSP_PCR_CLKRP_FALLING /* When the CLKR pin is configured as an input, the external CLKR is not */<br /> /* inverted before being used internally and the receive data is sampled on the */<br /> /* falling edge of CLKR. */<br /> ),<br /> MCBSP_RCERA_DEFAULT, <br /> MCBSP_RCERB_DEFAULT, <br /> MCBSP_RCERC_DEFAULT, <br /> MCBSP_RCERD_DEFAULT, <br /> MCBSP_RCERE_DEFAULT, <br /> MCBSP_RCERF_DEFAULT, <br /> MCBSP_RCERG_DEFAULT, <br /> MCBSP_RCERH_DEFAULT, <br /> MCBSP_XCERA_DEFAULT,<br /> MCBSP_XCERB_DEFAULT,<br /> MCBSP_XCERC_DEFAULT,<br /> MCBSP_XCERD_DEFAULT, <br /> MCBSP_XCERE_DEFAULT,<br /> MCBSP_XCERF_DEFAULT, <br /> MCBSP_XCERG_DEFAULT,<br /> MCBSP_XCERH_DEFAULT <br /> };<br /><br /><br /><br /><br /><br /><br />/* Create DMA Receive Side Configuration */<br /><br />/* DMACSDP dstben == 0 */<br />/* dstpack == 0 */<br />/* dst == 0 */<br />/* srcben == 0 */<br />/* srcpack == 0 */<br />/* src == 5 */<br />/* datatype == 1 */<br />/* */<br />/* DMACCR dstamode == 1 */<br />/* srcamode == 0 */<br />/* endprog == 0 */<br />/* repeat == 0 */ <br />/* autoinit == 1 */<br />/* en == 0 */<br />/* prio == 0 */<br />/* fs == 0 */<br />/* sync == 0 */<br />/* */<br />/* DMACICR blockie == 0 */<br />/* lastie == 0 */<br />/* frameie == 1 */<br />/* firsthalfie == 0 */<br />/* dropie == 0 */<br />/* timeoutie == 0 */<br />DMA_Config dmaRcvConfig = { <br /> DMA_DMACSDP_RMK(<br /> DMA_DMACSDP_DSTBEN_NOBURST, /* dest NO burst */<br /> DMA_DMACSDP_DSTPACK_OFF, /* DST Packing disabled */<br /> DMA_DMACSDP_DST_DARAM, /* DST is DARAM */<br /> DMA_DMACSDP_SRCBEN_NOBURST, /* source NO burst */<br /> DMA_DMACSDP_SRCPACK_OFF, /* source Packing disabled*/<br /> DMA_DMACSDP_SRC_PERIPH, /* source is PERIPH, McBSP0(RCV)*/<br /> DMA_DMACSDP_DATATYPE_16BIT<br /> ), /* DMACSDP */<br /> DMA_DMACCR_RMK( /* chanel control register */<br /> DMA_DMACCR_DSTAMODE_DBLINDX, /*After each element transfer, the address is incremented according to the selected data type:*/<br /> DMA_DMACCR_SRCAMODE_CONST, /*Constant address*/<br /> DMA_DMACCR_ENDPROG_ON, /* 1 */<br /> DMA_DMACCR_REPEAT_ON, /*Repeat only if ENDPROG = 1*/<br /> DMA_DMACCR_AUTOINIT_ON, /*Auto-initialization is enabled*/<br /> DMA_DMACCR_EN_START, /*1, Channel is enabled*/<br /> DMA_DMACCR_PRIO_LOW, /* */<br /> DMA_DMACCR_FS_ELEMENT, /* event occurs, one element transfered */ <br /> DMA_DMACCR_SYNC_REVT0 /* McBSP 0 receive event */<br /> ), /* DMACCR */<br /> DMA_DMACICR_RMK( /* interrupt control register */<br /> DMA_DMACICR_BLOCKIE_OFF, /* address error interrupt off */<br /> DMA_DMACICR_LASTIE_OFF,<br /> DMA_DMACICR_FRAMEIE_ON, /* when all of current frame transfer complete, send int to cpu */<br /> DMA_DMACICR_FIRSTHALFIE_OFF,<br /> DMA_DMACICR_DROPIE_OFF,<br /> DMA_DMACICR_TIMEOUTIE_OFF<br /> ), /* DMACICR */<br /> (DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL, lower part, Data Receive Register 1, McBSP #0 */<br /> 0, /* DMACSSAU source start address upper part*/<br /> (DMA_AdrPtr)&rcv[0], /* DMACDSAL; Destination Start Address Registers lower part */<br /> 0, /* DMACDSAU upper part*/<br /> (TS-1), /* DMACEN; numbr of element per Frame */<br /> 1, /* DMACFN; frame number per block */<br /> 0, /* DMACFI; source frame index */<br /> 0, /* DMACEI; source element index */<br /> 0,   |
|
楼主
