library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity multip4 is
port ( a,b:in std_logic_vector(3 downto 0);
c:out std_logic_vector(7 downto 0);
M:out std_logic_vector(3 downto 0)
);
end multip4;
architecture a of multip4 is
begin
M <= "0001";
c <= a*b;
end a;
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