LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY comp IS
PORT ( A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK: IN STD_LOGIC;
RST: IN STD_LOGIC;
AGTB: OUT STD_LOGIC;
ALTB: OUT STD_LOGIC;
AEQB: OUT STD_LOGIC;
M: out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END comp;
ARCHITECTURE arch OF comp IS
BEGIN
M <= "0001";
PROCESS (RST,CLK)
BEGIN
IF RST = '0' THEN
AGTB <= '0'; AEQB <= '0'; ALTB <= '0';
ELSIF CLK'EVENT AND CLK = '1' THEN
IF A > B THEN
AGTB <= '1'; AEQB <= '0'; ALTB <= '0';
ELSIF a = b THEN
AGTB <= '0'; AEQB <= '1'; ALTB <= '0';
else
AGTB <= '0'; AEQB <= '0'; ALTB <= '1';
END IF;
END IF;
END PROCESS;
END ARCH ;
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