大家好，我用DSP2812的ZONE0与FPGA通信（2812主频150M，FPGA 30M），采用读地址的方式（地址线低8位，数据线16位与FPGA相连），采用如下方式：#define data 0x002001；
buffer = *（int*）data；
但是DSP经常读到不正确的数，而且在读之前加延时还会影响读数正误，是不是我xintf设置的不对那，请大家帮我分析下！！谢谢！
如下是我的XINTF设置：
// All Zones:
// Timing for all zones based on XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.XTIMCLK = 1; // XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.CLKOFF = 1; // DISABLE XCLKOUT
XintfRegs.XINTCNF2.bit.WRBUFF = 0; // NO WRITE BUFFER
XintfRegs.XINTCNF2.bit.CLKMODE = 1; // XCLKOUT = XTIMCLK/4
// Zone 0
// Ignore XREADY for Zone 1 accesses
// Change read access lead/active/trail timing
XintfRegs.XTIMING0.bit.USEREADY = 0;
XintfRegs.XTIMING0.bit.XSIZE = 3; // ALWAYS WRITE TO 11BIT
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL=3;//修改，只有两位
XintfRegs.XTIMING0.bit.XWRLEAD=3;
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE =7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
// Double lead/active/trial timing for Zone 1
XintfRegs.XTIMING0.bit.X2TIMING=1; |
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