entity fenpin is
port( clk: in std_logic;
q: out std_logic)end fenpin;
architecture s1 of fenpin is
signal p :std_logic;
signal a:std_logic_vector(2 downto 0);
begin
process(clk)
--variable a:std_logic_vector(2 downto 0);
begin
if clk'event and clk='1' then
if a="111" then
a<="000";
p<=not p;
else
a<=a+1;
end if;
q<=p;
end if;
end process;
end s1; |
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