MSP430F41X/42X的头文件和43X,44X的不一样啊,没有以下的定义啊,那怎样才能设置成MCLK=ACLK=LFXT1啊?????
#define SELM_DCO (0x00) /* Select DCO for CPU MCLK */
#define SELM_XT2 (0x10) /* Select XT2 for CPU MCLK */
#define SELM_A (0x18) /* Select A (from LFXT1) for CPU MCLK */
#define SMCLKOFF (0x40) /* Peripheral Module Clock (SMCLK) disa××e */
用FLL通过D*(N+1)来做,结果SCFI0里面又没有32.768K的低频范围选择啊!!!!!
#define SCFI0_ (0x0050) /* System Clock Frequency Integrator 0 */
DEFC( SCFI0 , SCFI0_)
#define FN_2 (0x04) /* fDCOCLK = 1.4-12MHz*/
#define FN_3 (0x08) /* fDCOCLK = 2.2-17Mhz*/
#define FN_4 (0x10) /* fDCOCLK = 3.2-25Mhz*/
#define FN_8 (0x20) /* fDCOCLK = 5-40Mhz*/
头痛啊,哪位大虾给个解答啊,跪求!!!!!!!
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