module TIME3(
clk_36M,
clk
);
input clk_36M;
output clk;
reg[24:0] count; //分频计数器
reg div_clk;
wire clk_36M;
wire clk;
always @(posedge clk_36M）
begin
if(count==18000000)
begin
div_clk<=~div_clk;
count<=0;
end
else
count<=count+1;
clk<=div_clk;
end
endmodule
报错：ERROR:HDLCompilers:26 - "TIME3.v" line 31 unexpected token: 'clk_36M'
ERROR:HDLCompilers:26 - "TIME3.v" line 39 expecting 'endmodule', found 'else'
. |
|
楼主
